Spartan-3 FPGA Family: Functional Description
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are \others, indicated by the term \Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0, M1, and M2 are Dedicated pins. The mode pin settings are shown in Table26.Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode(1)Master Serial Slave SerialMaster Parallel Slave Parallel JTAGNotes:
1.2.
The voltage levels on the M0, M1, and M2 pins select the configuration mode.The daisy chain is possible only in the Serial modes when DOUT is used.
M001101
M101110
M201011
Synchronizing Clock
CCLK OutputCCLK InputCCLK OutputCCLK Input TCKInput
Data Width
11881
Serial DOUT(2)
YesYesNoNoNo
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.Table27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits. See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.Table 27:Spartan-3 FPGA Configuration Data
DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
File Sizes439,2641,047,6161,699,1363,223,4885,214,7847,673,02411,316,86413,271,936
Xilinx Platform Flash PROM
Serial Configuration
XCF01SXCF01SXCF02SXCF04SXCF08PXCF08PXCF16PXCF16P
Parallel Configuration
XCF08PXCF08PXCF08PXCF08PXCF08PXCF08PXCF16PXCF16P
The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4Gbits), roughly equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3 devices are available in two speed grades: –4 and the higher performance –5. Switching characteristics in this document may be designated as Advance, Preliminary, or Production. Each category is defined as follows:
Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reported delays may still occur.
Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data.
Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.
Production-quality systems must use FPGA designs compiled using a Production status speed file. FPGAs designs using a less mature speed file designation may only be used during system prototyping or preproduction qualification. FPGA designs using Advance or Preliminary status speed files should never be used in a production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the Xilinx ISE software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.
All specified limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the following applies: Parameter values apply to all Spartan-3 devices. All parameters representing voltages are measured with respect to GND.
Selected timing parameters and their representative values are included below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3 FPGA v1.38 speed files are the original source for many but not all of the values. The v1.38 speed files are available in Xilinx Integrated Software Environment (ISE) software version 8.2i.
The speed grade designations for these files are shown in Table 39. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.
Table 39: Spartan-3 FPGA Speed Grade Designations (ISE v8.2i or Later)
DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
-4, -5 (v1.38 andlater)
AdvancePreliminaryProduction-4, -5 (v1.37 andlater)
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 70:Spartan-3 FPGA Pin Definitions
Pin Name
I/O: General-purpose I/O pinsI/O
User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output
User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output
DirectionDescription
User I/O:
Unrestricted single-ended user-I/O pin. Supports all I/O standards except the differential standards.
User I/O, Half of Differential Pair:
Unrestricted single-ended user-I/O pin or half of a differential pair. Supports all I/O standards including the differential standards.
I/O_Lxxy_#
DUAL: Dual-purpose configuration pinsIO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1, IO_Lxxy_#/D2, IO_Lxxy_#/D3, IO_Lxxy_#/D4, IO_Lxxy_#/D5, IO_Lxxy_#/D6, IO_Lxxy_#/D7IO_Lxxy_#/CS_B
Input during configuration
Possible bidirectional I/O after configuration if SelectMap port is retained
Otherwise, user I/O after configuration
Input during Parallel mode configuration
Possible input after configuration if SelectMap port is retainedOtherwise, user I/O after configuration
Input during Parallel mode configuration
Possible input after configuration if SelectMap port is retainedOtherwise, user I/O after configuration
Output during configurationPossible output after
configuration if SelectMap port is retained
Otherwise, user I/O after configuration
Configuration Data Port:
In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained via the Persist bitstream option.
In Serial modes, DIN (D0) serves as the single configuration data input. This pin becomes a user I/O after configuration unless retained by the Persist bitstream option.
Chip Select for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Chip Select signal. This pin becomes a user I/O after configuration unless the SelectMAP port is retained via the Persist bitstream option.
IO_Lxxy_#/RDWR_B
Read/Write Control for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Write Enable, active-High Read Enable signal. This pin becomes a user I/O after configuration unless the SelectMAP port is retained via the Persist bitstream option.
Configuration Data Rate Control for Parallel Mode, Serial Data Output for Serial Mode:
In Parallel (SelectMAP) modes, BUSY throttles the rate at which configuration data is loaded. This pin becomes a user I/O after configuration unless the SelectMAP port is retained via the Persist bitstream option.
In Serial modes, DOUT provides preamble and configuration data to downstream devices in a multi-FPGA daisy-chain. This pin becomes a user I/O after configuration.
IO_Lxxy_#/BUSY/DOUT
IO_Lxxy_#/INIT_B
Bidirectional (open-drain) during Initializing Configuration Memory/Detected Configuration Error:configurationWhen Low, this pin indicates that configuration memory is being cleared. User I/O after configurationWhen held Low, this pin delays the start of configuration. After this pin is
released or configuration memory is cleared, the pin goes High. During configuration, a Low on this output indicates that a configuration data error occurred. This pin always has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM during configuration, regardless of the HSWAP_EN pin. This pin becomes a user I/O after configuration.
DCI: Digitally Controlled Impedance reference resistor input pinsIO_Lxxy_#/VRN_# or IO/VRN_#
Input when using DCIOtherwise, same as I/O
DCI Reference Resistor for NMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected between this pin and the VCCO supply for this bank. Otherwise, this pin is a user I/O.
DCI Reference Resistor for PMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected between this pin and the ground supply. Otherwise, this pin is a user I/O.
IO_Lxxy_#/VRP_# or IO/VRP_#
Input when using DCIOtherwise, same as I/O
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S200E-7FG456C中文规格书 - 图文
