MEMORY存储芯片MT48H32M16LFBF-75 ITB中文规格书 - 图文

Table 1: Key Timing Parameters

Data Rate (MT/s)Speed Grade-187E-25E-25-3CL = 3400400400400CL = 4533533533533CL = 5800800667667CL = 6800800800n/aCL = 71066n/an/an/atRC (ns)54555555Table 2: Addressing

ParameterConfigurationRefresh countRow addressBank addressColumn address256 Meg x 432 Meg x 4 x 8 banks8KA[13:0] (16K)BA[2:0] (8)A[11, 9:0] (2K)128 Meg x 816 Meg x 8 x 8 banks8KA[13:0] (16K)BA[2:0] (8)A[9:0] (1K)64 Meg x 168 Meg x 16 x 8 banks8KA[12:0] (8K)BA[2:0] (8)A[9:0] (1K)Figure 1: 1Gb DDR2 Part Numbers

Example Part Number: MT47H128M8SH-25:M-MT47HConfigurationPackageSpeed:RevisionConfiguration256 Meg x 4128 Meg x 864 Meg x 16PackagePb-free84-ball 8mm x 12.5mm FBGA60-ball 8mm x 10.0mm FBGA84-ball 8mm x 12.5mm FBGA60-ball 8mm x 10.0mm FBGALead solder84-ball 8mm x 12.5mm FBGA60-ball 8mm x 10mm FBGAHWJNHRCFNFSH256M4128M864M16L Low powerITIndustrial temperature-187E-25E-25-3 Speed GradetCK = 1.875ns, CL = 7tCK = 2.5ns, CL = 5tCK = 2.5ns, CL = 6tCK = 3ns, CL = 5Note:1.Not all speeds and configurations are available in all packages.

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1GbDDR2.pdf – Rev. Y 02/14 EN

{ :H/:M RevisionPreliminary

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

Functional Description

The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-tion. The double data rate architecture is essentially a 4n-prefetch architecture, with aninterface designed to transfer two data words per clock cycle at the I/O balls. A singleREAD or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, two-clock-cycle data transfer at the internal DRAM core and four correspondingn-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, foruse in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAMduring READs and by the memory controller during WRITEs. DQS is edge-aligned withdata for READs and center-aligned with data for WRITEs. The x16 offering has two datastrobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,UDQS#).

The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CKgoing HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-mands (address and control signals) are registered at every positive edge of CK. Inputdata is registered on both edges of DQS, and output data is referenced to both edges ofDQS as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-lected location and continue for a programmed number of locations in a programmedsequence. Accesses begin with the registration of an ACTIVATE command, which is thenfollowed by a READ or WRITE command. The address bits registered coincident withthe ACTIVATE command are used to select the bank and row to be accessed. The ad-dress bits registered coincident with the READ or WRITE command are used to selectthe bank and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write burst lengths of four oreight locations. DDR2 SDRAM supports interrupting a burst read of eight with anotherread or a burst write of eight with another write. An auto precharge function may be en-abled to provide a self-timed row precharge that is initiated at the end of the burst ac-cess.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAMenables concurrent operation, thereby providing high, effective bandwidth by hidingrow precharge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strengthoutputs are SSTL_18-compatible.

Industrial Temperature

The industrial temperature (IT) option, if offered, has two simultaneous requirements:ambient temperature surrounding the device cannot be less than –40°C or greater than85°C, and the case temperature cannot be less than –40°C or greater than 95°C. JEDECspecifications require the refresh rate to double when TC exceeds 85°C; this also requiresuse of the high-temperature self refresh option. Additionally, ODT resistance, input/output impedance and IDD values must be derated when TC is < 0°C or > 85°C.

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1GbDDR2.pdf – Rev. Y 02/14 EN

Preliminary

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

General Notes

?The functionality and the timing specifications discussed in this data sheet are for theDLL-enabled mode of operation.

?Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQterm is to be interpreted as any and all DQ collectively, unless specifically stated oth-erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the up-per byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.

?A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to beused, use the lower byte for data transfers and terminate the upper byte as noted:––––

Connect UDQS to ground via 1kΩ* resistorConnect UDQS# to VDD via 1kΩ* resistorConnect UDM to VDD via 1kΩ* resistor

Connect DQ[15:8] individually to either VSS or VDD via 1kΩ* resistors, or floatDQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

Table 39: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6 apply to the entire tableCurrent StateCS#RAS#CAS#AnyIdleRowactive, active,or prechargeHLXLLLLRead (autoprechargedisabled)LLLLWrite (autoprechargedisabled)LLLLRead (withautoprecharge)LLLLWrite (withautoprecharge)LLLLNotes:

XHXLHHLLHHLLHHLLHHLLHHLXHXHLLHHLLHHLLHHLLHHLLHWE#XHXHHLLHHLLHHLLHHLLHHLLCommand/ActionDESELECT (NOP/continue previous operation)NO OPERATION (NOP/continue previous operation)Any command otherwise allowed to bank mACTIVATE (select and activate row)READ (select column and start READ burst)WRITE (select column and start WRITE burst)PRECHARGEACTIVATE (select and activate row)READ (select column and start new READ burst)WRITE (select column and start WRITE burst)PRECHARGEACTIVATE (select and activate row)READ (select column and start READ burst)WRITE (select column and start new WRITE burst)PRECHARGEACTIVATE (select and activate row)READ (select column and start new READ burst)WRITE (select column and start WRITE burst)PRECHARGEACTIVATE (select and activate row)READ (select column and start READ burst)WRITE (select column and start new WRITE burst)PRECHARGE7, 10777, 87, 9, 10777, 877Notes1.This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been

met (if the previous state was self refresh).

2.This table describes an alternate bank operation, except where noted (the current stateis for bank n and the commands shown are those allowed to be issued to bank m, as-suming that bank m is in such a state that the given command is allowable). Exceptionsare covered in the notes below.3.Current state definitions:

Idle:Row active:Read:Write:

The bank has been precharged, tRP has been met, and any READburst is complete.

A row in the bank has been activated and tRCD has been met.No data bursts/accesses and no register accesses are in progress.A READ burst has been initiated with auto precharge disabledand has not yet terminated.

A WRITE burst has been initiated with auto precharge disabledand has not yet terminated.

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

READ with autoprecharge enabled/WRITE with autoprecharge enabled:

The READ with auto precharge enabled or WRITE with auto pre-charge enabled states can each be broken into two parts: the ac-cess period and the precharge period. For READ with auto pre-charge, the precharge period is defined as if the same burst wasexecuted with auto precharge disabled and then followed withthe earliest possible PRECHARGE command that still accesses allof the data in the burst. For WRITE with auto precharge, the pre-charge period begins when tWR ends, with tWR measured as ifauto precharge was disabled. The access period starts with regis-tration of the command and ends where the precharge period(or tRP) begins. This device supports concurrent auto prechargesuch that when a READ with auto precharge is enabled or aWRITE with auto precharge is enabled, any command to otherbanks is allowed, as long as that command does not interruptthe read or write data transfer already in process. In either case,all other related limitations apply (contention between read da-ta and write data must be avoided).

4.5.6.7.8.9.10.

The minimum delay from a READ or WRITE command with auto precharge enabled toa command to a different bank is summarized in Table 40 (page 77).

REFRESH and LOAD MODE commands may only be issued when all banks are idle.Not used.

All states and sequences not shown are illegal or reserved.

READs or WRITEs listed in the Command/Action column include READs or WRITEs withauto precharge enabled and READs or WRITEs with auto precharge disabled.A WRITE command may be applied after the completion of the READ burst.Requires appropriate DM.

The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whicheveris greater.

Table 40: Minimum Delay with Auto Precharge Enabled

From Command (Bank n)WRITE with auto prechargeTo Command (Bank m)READ or READ with auto prechargeWRITE or WRITE with auto prechargePRECHARGE or ACTIVATEREAD with auto prechargeREAD or READ with auto prechargeWRITE or WRITE with auto prechargePRECHARGE or ACTIVATEMinimum Delay(with Concurrent Auto Precharge)(CL - 1) + (BL/2) + tWTR(BL/2)1(BL/2)(BL/2) + 21UnitstCKtCKtCKtCKtCKtCKDESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed bythe DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already inprogress are not affected. DESELECT is also referred to as COMMAND INHIBIT.

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