好文档 - 专业文书写作范文服务资料分享网站

FPGA可编程逻辑器件芯片XC2V6000-6BG728I中文规格书

天下 分享 时间: 加入收藏 我要投稿 点赞

TX Gearbox

External Sequence Counter Operating Mode

As shown in Figure6-12, the external sequence counter operating mode uses the

TXSEQUENCE(0/1)[6:0], TXDATA(0/1)[31:0], and TXHEADER(0/1)[2:0] inputs. A binary counter must exist in the user logic to drive the TXSEQUENCE(0/1) input port. For

64B/66B encoding, the counter increments from 0 to 32 and repeats from 0. For 64B/67B encoding, the counter increments from 0 to 66 and repeats from 0. When using 64B/66B encoding, tie TXSQUENCE(0/1)[6] to a logic 0 and tie the unused TXHEADER(0/1)[2] to a logic 0. The sequence counter increment ranges ({0 to 32}, {0 to 66}) are identical for both the 2-byte and 4-byte interfaces. However, the counter must increment once every two TXUSRCLK2 cycles when using a 2-byte interface and every TXUSRCLK2 cycle when using a 4-byte interface.

X-Ref Target - Figure 6-12Design in FPGA LogicTXDATA[15:0] or TXDATA[31:0]Data SourceTX Gearbox(in GTX Transceiver)TXHEADER[2:0]PauseTXSEQUENCE[6:0]Sequence Counter0-32 or 0-66UG198_c6_12_110107Figure 6-12:TX Gearbox in External Sequence Counter Mode

Due to the nature of the 64B/66B and 64B/67B encoding schemes, user data is held (paused) during various sequence counter values. Data is then paused for two

TXUSRCLK2 cycles in 2-byte mode and for one TXUSRCLK2 cycle in 4-byte mode. Valid data transfer is resumed on the next TXUSRCLK2 cycle. The data pause only applies to TXDATA(0/1) and not to TXHEADER(0/1).??

64B/67B encoding: data is held (paused) for sequence counter values of 21, 44, and 65.64B/66B encoding, data is held (paused) at counter value 31.

Figure6-13 shows how a pause occurs at counter value 31 when using a 4-byte interface, external sequence counter mode, and 64B/66B encoding.

X-Ref Target - Figure 6-13TXUSRCLK20TXHEADER01TXSEQUENCE0-24TXDATA02526272829303132012324156-87964daa629a14708d14111ae38287118777acf17c5804984e1fea87120459d55714e976523cd41353365af54e658bf8d3892141c1a9308dPause for 1 USRCLK2 cycle. Data is ignored.UG198_c6_13_101907Figure 6-13:Pause at Sequence Counter Value 31

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

Chapter 6:GTX Transmitter (TX)

Configurable TX Driver

Overview

The GTX TX driver is a high-speed current-mode differential output buffer. To maximize signal integrity, it includes these features:???

Differential voltage controlPre-emphasis

Configurable termination impedance

The impact of each of these features on signal integrity depends on the board and the receiver. See Chapter10, “GTX-to-Board Interface,” for a detailed discussion of how to use them to maximize signal integrity. Figure6-22 shows the different segments of the TX driver.

X-Ref Target - Figure 6-22MGTAVTTTXTXPREEMPHASIS[3:0]MGTTXNPre-DriverMainPad DriverMGTTXPTxData[19:0]PISO20:1TXBUFDIFFCTRL[2:0]TXDIFFCTRL[2:0]Pre-DriverTX Serial ClockPre-emphasisPad DriverTXPREEMPHASIS[3:0]UG198_c6_22_101207Notes: 1.TXPREEMPHASIS[3] is always 0.

Figure 6-22:TX Driver Segments

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

TX Out-of-Band/Beacon Signaling

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

FPGA可编程逻辑器件芯片XC2V6000-6BG728I中文规格书

TXGearboxExternalSequenceCounterOperatingModeAsshowninFigure6-12,theexternalsequencecounteroperatingmodeusestheTXSEQUENCE(0/1)[6:0],TXDATA(0/1)[31:0],andTXH
推荐度:
点击下载文档文档为doc格式
3c0tb6xycd7l7tx29ybm0wacw0f2i000gd6
领取福利

微信扫码领取福利

微信扫码分享