SelectMAP Configuration Interface
BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.
Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.
SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.
In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle
12
Notes:
1.D[0:7] represent the SelectMAP DATA pins.
Hex Equivalent
0xAB0xCD
D011
D101
D210
D300
D411
D501
D610
D711
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).
Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.
Virtex-5 Modex32x16x8
Pin
3130292827262524232221201918171615141312111024252627282930311617181920212223
88
99
9
8
7000
6111
5222
4333
3444
2555
1666
0777
101112131415101112131415
Virtex-4x32 Mode
31302928272625242322212019181716151413121110
9
8
7
6
5
4
3
2
1
0
Figure 2-19:Bit Ordering
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
SPI Configuration Interface
In SPI serial Flash mode, M[2:0]=001. The Virtex-5 FPGA configures itself from an attached industry-standard SPI serial Flash PROM. Although SPI is a standard four-wire interface, various available SPI Flash memories use different read commands and protocol. Besides M[2:0], FS[2:0] pins are sampled by the INIT_B rising edge to determine the type of read commands used by SPI Flash (see Table2-8). For Virtex-5 FPGA configurations, the default address always starts from 0. Figure2-20 shows the SPI related configuration pins, and the standard connection between Virtex-5 devices and SPI Flash.
4.7 kΩVirtex-5 FPGA330ΩINIT_BPROGRAM_BHSWAPEN Select SPI variantwith pull-up orpull-down resistorsM[2:0]FS[2:0]DONESPI FlashCLKCS_BDIDOUTCCLKFCS_BMOSID_INDOUG191_c2_23_072407Figure 2-20:Virtex-5 Device SPI Configuration Interface
Notes related to Figure2-20:??????
FCS_B and MOSI are clocked by the CCLK falling edge.D_IN is clocked on the rising edge of the CCLK.CCLK and D_IN are dedicated Configuration I/Os.
FCS_B is a dual-mode I/O. MOSI is a dual-mode I/O, muxed with FOE_B. FS[2:0] aredual-mode I/Os sampled on the INIT_B rising edge, muxed with D[2:0].
The internal I/O pull-up resistors should be enabled for FCS_B, MOSI, and D_IN.There are additional pins on the SPI Flash side, such as Write Protect and Hold. Thesepins are not used in FPGA configuration (read only). But they should be tied offappropriately according to the SPI vendor’s specification.
If HSWAPEN is left unconnected or tied High, a pull-up resistor is required for FCS_Band MOSI.
If HSWAPEN is tied Low, the FCS_B and MOSI pins have internal weak pull-upresistors during configuration. After configuration, FCS_B and MOSI can be eithercontrolled by I/O in user mode or by enabling a weak pull-up resistor throughconstraints.
HSWAPEN must be connected to either disable or enable the pull-up resistors.CCLK always has a weak internal pull-up resistor. The CCLK frequency can beadjusted using the ConfigRate BitGen option.
To enable the active driver on DONE, the DriveDONE option in BitGen must beenabled.
??
???
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Byte Peripheral Interface Parallel Flash Mode
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type
Dedicated or Dual-Purpose
Description
Pin Name INIT_B
Input or Dedicated Before the Mode pins are sampled, INIT_B is an input that can be held Output, Low to delay configuration. After the Mode pins are sampled, INIT_B Open-Drain is an open-drain, active-Low output indicating whether a CRC error
occurred during configuration:
0 = CRC error 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
CCLK Output
Dedicated Configuration clock output. CCLK does not directly connect to BPI
Flash but is used internally to generate the address and sample read data. Dual
Active-Low Flash chip select output. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash output enable. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash write enable. This output is actively driven High during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Address output. For I/O bank locations, see Table1-2, page17.
FCS_BOutput
FOE_B Output Dual
FWE_BOutputDual
ADDR[25:0]OutputDual
D[15:0]InputDual
Data input, sampled by the rising edge of the FPGA CCLK. For I/O bank location, see Table1-2, page17.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Board Layout for Configuration Clock (CCLK)
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S15-5FGG256C中文规格书 - 图文
