FPGA可编程逻辑器件芯片XC2V80-6FG456C中文规格书 - 图文

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SelectMAP Configuration Interface

PROM files for ganged serial configuration are identical to the PROM files used to configure single devices. There are no special PROM file considerations.

SelectMAP Configuration Interface

The SelectMAP configuration interface (Figure2-6) provides an 8-bit, 16-bit, or 32-bit bidirectional data bus interface to the Virtex-5 configuration logic that can be used for both configuration and readback. (For details, refer to Chapter7, “Readback and Configuration Verification.”) The bus width of SelectMAP is automatically detected (see “Bus Width Auto Detection”).

CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. One or more Virtex-5 devices can be configured through the SelectMAP bus.There are four methods of configuring an FPGA in SelectMAP mode:????

Single device Master SelectMAPSingle device Slave SelectMAPMultiple device SelectMAP busMultiple device ganged SelectMAP

M[2:0] D[31:0]INIT_B PROGRAM_BRDWR_B CS_B DONE CCLK UG191_c2_10_072407

BUSY CSO_BFigure 2-6:Virtex-5 Device SelectMAP Configuration Interface

Table2-4 describes the SelectMAP configuration interface.

Table 2-4:Virtex-5 Device SelectMAP Configuration Interface PinsPin Name

M[2:0]CCLK

Type

InputInput and OutputThree-State Bidirectional

Dedicated or Dual-Purpose

DedicatedDedicatedDual-Purpose

Description

Mode pins - determine configuration modeConfiguration clock source for all configuration modes except JTAG

D[31:0]

Configuration and readback data bus, clocked on the rising edge of CCLK. See “Parallel Bus Bit Order” and Table1-2.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

SelectMAP Configuration Interface

Single Device SelectMAP Configuration

High-Performance Platform Flash XL SelectMAP Configuration

The Platform Flash XL is specially optimized for high-performance Virtex-5 FPGA configuration and ease-of-use. Platform Flash XL integrates 128Mb of in-system programmable flash storage and performance features for configuration within a small-footprint FT64 package. Power-on burst read mode and dedicated I/O power supply enable Platform Flash XL to mate seamlessly with the Virtex-5 FPGA SelectMAP configuration interface. A wide, 16-bit data bus delivers the FPGA configuration bitstream at speeds to 800Mb/s without wait states. A simplified model of the Platform Flash XL configuration solution for a Virtex-5 FPGA is shown in Figure2-7.

Platform Flash XLREADY_WAITConfigurationSynchronizationHandshakeVirtex-5 FPGAClock up to 50 MHzFPGA Design(.bit) FileWide (16-bit) DatapathUp to 800 Mb/sSelectMAPPortUG191_c2_28_051208

Figure 2-7:Platform Flash XL High-Performance FPGA Configuration

For Virtex-5 FPGA configuration, the Platform Flash XL takes advantage of the 16-bit SelectMAP feature to accomplish high-speed configuration. Minimal configuration time is achieved with an external, free-running oscillator driving the configuration clock in Slave SelectMAP mode. For Platform Flash XL details, see DS617, Platform Flash XL High-Density Configuration and Storage Device data sheet.

After configuration, the Virtex-5 FPGA can access any remaining memory space, beyond the bitstream, in the Platform Flash XL. The Platform Flash XL has a standard BPI NOR Flash interface. In addition to the 16-bit data bus, which is dually used for SelectMAP configuration, the Platform Flash XL has a standard address bus and read/write control pins for random access reads and for sending CFI-compliant commands.

For prototype designs, the ISE? iMPACT software provides an indirect Platform Flash XL programming solution through the IEEE Standard 1149.1 (JTAG) port of the

Virtex-5FPGA. The iMPACT software downloads a pre-built design bitstream into the Virtex-5FPGA that bridges the FPGA JTAG port to the FPGA BPI Flash configuration interface. The FPGA BPI Flash configuration interface is a superset of the FPGA SelectMAP interface. When the Platform Flash XL's standard address and control pins are connected to the corresponding FPGA BPI Flash interface pins, the iMPACT indirect programming solution can program the Platform Flash XL with the prototype design bitstream, as shown in Figure2-8.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 2:Configuration Interfaces

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Board Layout for Configuration Clock (CCLK)

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

SelectMAP Configuration Interface

BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.

Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.

SelectMAP Data Ordering

In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is

important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.

In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle

Notes:

1.D[0:7] represent the SelectMAP DATA pins.

Hex Equivalent

0xAB0xCD

D011

D101

D210

D300

D411

D501

D610

D711

Some applications can accommodate the non-conventional data ordering without

difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).

Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.

Virtex-5 Modex32x16x8

3130292827262524232221201918171615141312111024252627282930311617181920212223

7000

6111

5222

4333

3444

2555

1666

0777

101112131415101112131415