Table 3. Register Address/Definition RTC
READ 81h 83h 85h 87h 89h 8Bh 8Dh 8Fh 91h
WRITE BIT 7 BIT 6 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h
CH 12/24 0 0 0 WP TCS
BIT 5
BIT 4
BIT 3 BIT 2 BIT 1
Seconds Minutes Hour Date Month
0 0 DS
Day Year 0 0 DS RS
BIT 0
RANGE 00–59
00–59 1–12/0–23 1–31 1–12 1–7 00–99 — —
10 Seconds 10 Minutes
10
0 Hour
AM/PM 0 10 Date
10
0 0
Month
0 0 0 10 Year 0 0 0 TCS TCS TCS
0
RS
CLOCK BURST
BFh
BEh
RAM
C1h C3h C5h ...FDh
C0h C2h C4h ...FCh
00-FFh00-FFh00-FFh..
.
00-FFh
RAM BURST
FFh
FEh
Figure 5. Programmable Trickle Charger
TRICKLE CHARGE REGISTER (90h write, 91h read)Bit 7TCS3Bit 6TCS2Bit 5TCS1Bit 4TCS0Bit 3DS1Bit 2DS0Bit 1ROUT1Bit 0ROUT0TCS0-3 = TRICKLE CHARGER SELECTDS0-1 = DIODE SELECTROUT0-1 = RESISTOR SELECT1 0F 16 SELECTNOTE: ONLY 1010b ENABLES CHARGER1 OF 2SELECT1 OF 3SELECTR1VCC22K?R24k?R38k?VCC1Figure 1. Block Diagram
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
DS1302 Trickle-Charge Timekeeping Chip
PIN DESCRIPTION
PIN
NAME
FUNCTION
Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Ground
Input. CE signal must be asserted high during a read or a write. This pin has an internal 40k? (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40k? (typ) pulldown resistor to ground.
Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40k? (typ) pulldown resistor to ground.
1 VCC2
2 X1
3 4 5
X2 GND CE
6 7
I/O SCLK
DS1302 Trickle-Charge Timekeeping Chip
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined.
WRITE-PROTECT BIT
Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device.
TRICKLE-CHARGE REGISTER
This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between VCC2 and VCC1. The resistor and diodes are selected by the RS and DS bits as shown in Table 2.
Table 2. Trickle Charger Resistor and Diode Select
TCS BIT 7
X X X 1 1 1 1 1 1 0
TCS BIT 6
X X X 0 0 0 0 0 0 1
TCS BIT 5
X X X 1 1 1 1 1 1 0
TCS BIT 4
X X X 0 0 0 0 0 0 1
DS BIT 3
X 0 1 0 0 0 1 1 1 1
DS BIT 2
X 0 1 1 1 1 0 0 0 1
RS BIT 1
0 X X 0 1 1 0 1 1 0
RS BIT 0
0 X X 1 0 1 1 0 1 0
FUNCTION
Disabled Disabled Disabled 1 Diode, 2k? 1 Diode, 4k? 1 Diode, 8k? 2 Diodes, 2k? 2 Diodes, 4k? 2 Diodes, 8k? Initial power-on state
Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would therefore be calculated as follows:
IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2k? ≈ 2.2mA
As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current decreases.
DS1302 Trickle-Charge Timekeeping Chip
Figure 6. Timing Diagram: Read Data Transfer
CEtCCtRtFSCLKtCLtCDHtDCI/OREAD DATA BYTEtCHtCDDtCCZtCDZADDRESS/COMMAND BYTEFigure 7. Timing Diagram: Write Data Transfer
CEtCWHtCCtRtFtCCHSCLKtCDHI/OtDCtCLtCHADDRESS/COMMAND BYTEWRITE DATA BYTECHIP INFORMATION
TRANSISTOR COUNT: 11,500
THERMAL INFORMATION
PACKAGE 8 DIP
8 SO (150 mils)
THETA-JA (°C/W) 110 170
THETA-JC (°C/W) 40 40
PACKAGE TYPE 8 PDIP 8 SO (208 mils) 8 SO (150 mils) PACKAGE CODE — — — DOCUMENT NO. 21-004321-026221-0041
MEMORY存储芯片DS1302Z-1中文规格书 - 图文
