.
////////////////////////////////////////////////////////
always(posedge clk) begin
if(read_enable)//当read_enable为高电平时为发送操作状态
begin
clk_enable3<=1; clear3<=clear1;
end
else
begin
clear3<=1;
end
end
//////////////////////////////////////////////////////////////////////////////
.
.
.
always(negedge counters[0]) ///接收操作 if(read_enable & !reset) begin if (counters==8'b00011000) //1 begin data_out[7]<=read;
parity_check_result<=parity_check_result + read;
end
else if (counters==8'b00101000) //2 begin data_out[6]<=read;
parity_check_result<=parity_check_result + read;
end
else if (counters==8'b00111000) //3
begin data_out[5]<=read;
parity_check_result<=parity_check_result + read;
end
.
.
else if (counters==8'b01001000) //4 begin data_out[4]<=read;
parity_check_result<=parity_check_result + read;
end
else if (counters==8'b01011000) //5 begin data_out[3]<=read;
parity_check_result<=parity_check_result + read;
end
else if (counters==8'b01101000) //6 begin data_out[2]<=read;
parity_check_result<=parity_check_result + read;
end
else if (counters==8'b01111000) //7 begin data_out[1]<=read;
parity_check_result<=parity_check_result + read;
.
end
else if (counters==8'b10001000) //8
begin
data_out[0]<=read;
parity_check_result<=parity_check_result + read; end
else if (counters==8'b10011000) //9进行奇偶校验检测
begin
parity_result<=#2
(parity_check_result
==
parity_result<=read;
parity_result) ? 1:0;
end
else if (counters==8'b10101000) //0进行帧检测
begin
cs1<=(read) ? 1:0;
end
else if (counters==8'b10101010) //01给cpu发送接收信号
begin
.
.
cs<=(cs1 && parity_result) ? 1:0;//当奇偶校验结果
与帧检测结果都为1时，cs置位
clear1<=1;
//clk_enable<=0; //clk_enable3<=0; end
else if(counters==8'b00001000)//检测是否是毛刺
begin
clear1<=(!read)?0:1; end
else clear1<=0; end
else clear1<=1;
endmodule
3.3.4UART的数据发送模块程序仿真图
当reset为零时
.
FPGA的UART完整设计
