Chapter 2: XPHY Architecture
Figure 12: 2-bit RX Datapath Latency when FIFO_MODE_x = ASYNC
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
Chapter 2: XPHY Architecture
Tristate Control
The XPHY can control buffers with tristate capability. The tristating can be performed on a per-NIBBLESLICE basis, as determined through the TBYTE_CTL_<0-5> attribute.
Controlling Tristate Control
Buffers with tristate capability can be controlled through the XPHY on a per-NIBBLESLICE basis,as determined through the TBYTE_CTL_<0-5> attribute. The <0-5> suffix of TBYTE_CTL_<0-5>corresponds to the NIBBLESLICE it is applied to. So TBYTE_CTL_0 is the tristate control settingfor NIBBLESLICE[0], TBYTE_CTL_1 corresponds to NIBBLESLICE[1], and so on.
?TBYTE_CTL_x = T: Uses the T[x] input of the XPHY to drive the tristate control signal to theIOB of NIBBLESLICE[x]. This is a combinatorial path from the PL and thus is not aligned to TXdata. When TX_DATA_WIDTH = 2, this is the only TBYTE_CTL_x setting supported.?TBYTE_CTL_x = PHY_WREN: Inverts and serializes the PHY_WREN input of the XPHY todrive (broadcast) the tristate control signal to the IOB of each NIBBLESLICE. Each bit ofPHY_WREN acts as the tristate control signal for two UIs worth of data. The serialized andinverted PHY_WREN signal is aligned to the serialized output of the TX datapath, O0.PHY_WREN cannot be used when TX_DATA_WIDTH = 2.TBYTE_CTL_x determines which signal, T or PHY_WREN, is accepted by NIBBLESLICE[x]. Forexample, if NIBBLESLICE[0] receives both a PHY_WREN and T stimulus, only the one matchingTBYTE_CTL_0 is accepted. T_OUT[x] is then the output to the IOB.
The latency through the TX datapath is shown for TBYTE_CTL_x = PHY_WREN. PHY_WRENtakes one cycle longer than the data to propagate through the XPHY. Due to this, PHY_WRENshould be applied one cycle before TX data is presented to the XPHY from the PL.
Note: Updates to the delay line in tristate control must be done through the RIU interface.
Independent of tristating, each bit of O0 maps to one of the D<0-5>[7:0] inputs. Generalized,this means Dx maps to O0[x]. The following tables shows how Dx maps to O0[x] for differentdata widths. Refer to the latency waveforms below for the context of P0, N0, …, P3, N3.Table 12: Dx to O0[x] Mapping
Serialization(TX_DATA_WIDTH)
8:1
Dx
Dx[7]
The
eighth bitserializedand
transmitted throughO0[x]
Dx[6]
Theseventhbit
serializedand
transmitted throughO0[x]
Dx[5]
The sixthbit
serializedand
transmitted throughO0[x]
Dx[4]
The fifthbit
serializedand
transmitted throughO0[x]
Dx[3]
The fourthbit
serializedand
transmitted throughO0[x]
Dx[2]
The thirdbit
serializedand
transmitted throughO0[x]
Dx[1]
The
second bitserializedand
transmitted throughO0[x]
Dx[0]
The firstbit
serializedand
transmitted throughO0[x]
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-6BG728I中文规格书
