3.Intel Agilex I/O Termination
UG-20244 | 2024.04.05
File NameDescription
Simulation caching file that compares the .qsys and .ip files with the currentparameterization of the Platform Designer system and IP. This comparisondetermines if Platform Designer can skip regeneration of the HDL.
Synthesis caching file that compares the .qsys and .ip files with the currentparameterization of the Platform Designer system and IP. This comparisondetermines if Platform Designer can skip regeneration of the HDL.Contains information about the upgrade status of the IP component.A symbol representation of the IP variation for use in Block Diagram Files(.bdf).
Input file that ip-make-simscript requires to generate simulation scripts.The .spd file contains a list of files you generate for simulation, along withinformation about memories that you initialize.
The Pin Planner File (.ppf) stores the port and node assignments for IPcomponents you create for use with the Pin Planner.
Use the Verilog blackbox (_bb.v) file as an empty module declaration for useas a blackbox.
HDL example instantiation template. Copy and paste the contents of this fileinto your HDL file to instantiate the IP variation.
If the IP contains register information, the Intel Quartus Prime softwaregenerates the .regmap file. The .regmap file describes the register mapinformation of master and slave interfaces. This file complements
the .sopcinfo file by providing more detailed register information about thesystem. This file enables register display views and user customizable statisticsin System Console.
Allows HPS System Debug tools to view the register maps of peripherals thatconnect to HPS within a Platform Designer system.
During synthesis, the Intel Quartus Prime software stores the .svd files forslave interface visible to the System Console masters in the .sof file in thedebug session. System Console reads this section, which Platform Designerqueries for register map information. For system slaves, Platform Designeraccesses the registers by name.
systems only)
Designer systems only)
/synopsys/vcs/synopsys/vcsmx/cadence/xcelium/submodules
HDL files that instantiate each submodule or child IP for synthesis orsimulation.
Contains a msim_setup.tcl script to set up and run a ModelSim simulation.Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run asimulation.
Contains a shell script vcs_setup.sh to set up and run a VCS simulation.Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file toset up and run a VCS MX simulation.
Contains a shell script ncsim_setup.sh and other setup files to set up andrun an NCSim simulation.
Contains an Xcelium Parallel simulator shell script xcelium_setup.sh andother setup files to set up and run a simulation.Contains HDL files for the IP submodule.
Platform Designer generates /synth and /sim sub-directories for each IPsubmodule directory that Platform Designer generates.
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3.Intel Agilex I/O TerminationUG-20244 | 2024.04.05
OCT Intel FPGA IP SignalsTable 35.
Input Interface Signals
In the table, n represents the number of OCT blocks defined in the Number of OCT blocks parameter.Signal Name
DirectionInput
Width1 per OCTblock
Description
Input connection from RZQ pad to the OCT block. RZQpad is connected to an external resistance. The OCTblock uses impedance connected to the rzqin port asa reference to generate the calibration code.
This signal is available for power-up and user modes.Set to 1 to request the OCT block to start calibration.Hold the signal for at least 2 ms or until ack_recal isset to 1.
This signal is only available for user mode.
When set to 1 indicates OCT block is ready for
calibration. There should be no calibration activitiesfrom the core to the OCT block until this signal isasserted for every calibration request.
This signal is only available for user mode.
Transfer serial output calibration data from OCT blockto I/O buffer.
rzqin[n:0]
calibration_request[n:0]Input
1 per OCTblock
ack_recal[n:0]Output
1 per OCTblock
ser_data_nOutput
1 per OCTblock
QSF Assignments
Intel Agilex devices support the following termination-related Intel Quartus Primesettings file (.qsf) assignments:????
Table 36.
INPUT_TERMINATIONOUTPUT_TERMINATION
TERMINATION_CONTROL_BLOCKRZQ_GROUP
QSF Assignments
DetailsThe input/output termination assignment specifies the termination value in ohm on the pinin question.Example:set_instance_assignment -name INPUT_TERMINATION
3.Intel Agilex I/O Termination
UG-20244 | 2024.04.05
QSF AssignmentExample:Detailsset_instance_assignment -name TERMINATION_CONTROL_BLOCK
Use a .qsf assignment to indicate which pin (bus) is associated with which OCTblock. You can use the TERMINATION_CONTROL_BLOCK assignment to associatesa pin with an OCT instantiated in the RTL.
Instantiate the I/O buffer primitives at the top level and connect them to theappropriate OCT blocks as shown in the following figure.
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Figure 39.
OCT Block Connection with I/O Buffer
Top Level RTLdin0din1rzqininput_buffer1ITERMINATIONCONTROLOCT blockRZQINSER_DATAOITERMINATIONCONTROLoutput_buffer1Oinput_bufferinput_buffer0ITERMINATIONCONTROLOITERMINATIONCONTROLdout0dout1output_bufferoutput_buffer0ONote:
All I/O banks within the same bank row with the same VCCIO can share one OCT blockeven if that particular I/O bank has its own OCT block. You can connect any number ofI/O pins that support calibrated termination to an OCT block. Ensure that you connectI/Os with compatible configuration to an OCT block. You must also ensure that theOCT block and its corresponding I/Os have the same VCCIO and series or paralleltermination values. With these settings, the Fitter places the I/Os and OCT block inthe same column. The Intel Quartus Prime software generates warning messages ifthere is no pin connected to the block.
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FPGA可编程逻辑器件芯片EP3C120F484C8中文规格书
