IW4069、CD4069、HEF4069类型包含六个逆变器电路。 这些器件适用于所有通用逆变器应用，这些应用不需要IW4069、CD4069、HEF4069十六进制反相器/缓冲器等电路的中等功率TTL驱动和逻辑电平转换功能。 六个逆变器中的每一个都是一个单级
Hex Inverter
High-Voltage Silicon-Gate CMOS
The IW4069、CD4069、HEF4069 types consist of six inverter circuits. These devices are intended for all general-purpose inverter applications where the medium-power TTL-drive and logic-level-conversion capabilities of circuits such as the IW4049UB Hex Inverter/Buffers are not required. Each of the six inverters is a single stage ?
Operating Voltage Range: 3.0 to 18 V工作电压范围：3.0至18 V 在整个封装温度范围内，18 V时的最大输入电流为1A。 在18 和25C下为100 nA
噪声容限（在整个封装温度范围内）：
最小0.5 V @ 5.0 V电源 最小1.0 V @ 10.0 V电源 最低1.5 V @ 15.0 V电源??
ORDERING INFORMATION
IW4069UBN Plastic IW4069UBD SOIC
TA = -55? to 125? C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE Inputs Output Y A L H L PIN 14 =VCC PIN 7 = GND
L – LOW voltage level
H
H – HIGH voltage level
Symbol ABSOLUTE MAXIMUM RATINGS*
Parameter Value Unit V VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 -0.5 to VCC +0.5 ?10 VIN IIN DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ V mA mW PD 500 500 100 Ptot Power Dissipation per Output Transistor Storage Temperature mW
Tstg -65 to +150 ?C *
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/?C from 100? to 125?C
SOIC Package: : - 7 mW/?C from 65? to 125?C
最大额定值是那些可能会损坏设备的值。 功能操作应限于建议的操作条件。 +降额-塑料DIP：-从100W到125 fromC为12 mW /°C
SOIC封装：：-从65°到125°C为7 mW /°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit V VCC DC Supply Voltage (Referenced to GND) 3.0 18 VCC VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 -55 V ?C TA Operating Temperature, All Package Types +125
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND?(VIN or VOUT)?VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
该设备包含保护电路，以防止由于高静电电压或电场而造成损坏。
但是，必须采取预防措施，以避免向该高阻抗电路施加高于最大额定电压的任何电压。 为了正常工作，VIN和VOUT应该限制在GND to（VIN或
VOUT）VCC。
未使用的输入必须始终连接到适当的逻辑电压电平（例如GND或VCC）。
未使用的输出必须保持打开状态。
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Guaranteed Limit Symbol Parameter Test Conditions V ?-55?C 25?C ?125 Unit ?C VIH VIL Minimum High-Level VOUT=0.5V VOUT=1.0 V Input Voltage VOUT=1.5V Maximum Low -Level VOUT= VCC - 0.5 V VOUT= VCC - 1 V Input Voltage VOUT= VCC - 1.5 V Minimum High-Level VIN=GND Output Voltage 5.0 10 15 5.0 10 15 5.0 10 15 4.0 8.0 12.5 1.0 2.0 2.5 4.95 9.95 14.95 4.0 8.0 12.5 1.0 2.0 2.5 4.95 9.95 14.95 4.0 V 8.0 12.5 1.0 V 2.0 2.5 4.95 V 9.95 14.95 VOH VOL Maximum Low-Level VIN= VCC Output Voltage 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V 0.05 0.05 IIN Maximum Input Leakage Current VIN= GND or VCC 18 ?0.1 ?0.1 ?1.0 ?A ICC Maximum Quiescent VIN= GND or VCC Supply Current (per Package) 5.0 10 15 20 0.25 0.5 1.0 5.0 0.25 0.5 1.0 5.0 7.5 ?A 15 30 150 IOL IOH
Minimum Output Low VIN= GND or VCC UOL=0.4 V (Sink) Current UOL=0.5 V UOL=1.5 V VIN= GND or VCC Minimum Output High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 mA 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 mA
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k?, Input tr=tf=20 ns)
VCC Guaranteed Limit V ?-55?C 25?C ?125?C Unit Symbol Parameter 110 tPLH, tPHL Maximum Propagation Delay, Input A to Output 5.0 110 110 ns Y (Figure 1) 10 15 60 50 60 50 80 80 200 100 80 tTLH, tTHL Maximum Output Transition Time, Any Output 5.0 (Figure 1) 10 15 200 100 80 200 100 80 15 ns CIN Maximum Input Capacitance - pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
INPUT/OUTPUT PROTECTION CIRCUIT
(for each element)
IKSEMI逻辑芯片6反相器电路IW4069 CD4069 HEF4069-奥伟斯 - 图文
