FPGA可编程逻辑器件芯片XCZU9EG-1FFVC900I中文规格书 - 图文

Introduction to the RocketIO GTX Transceiver

Overview

The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex?-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:???

Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.

Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.

Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.

Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.

Fixed latency modes for minimized, deterministic datapath latency.

Beacon signaling for PCI Express? designs and Out-of-Band signaling includingCOM signal support for SATA designs.

RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.Receiver eye scan:

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Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes

The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.

Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx? CORE Generator? tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).

The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

Chapter 6:GTX Transmitter (TX)

TX Gearbox

Overview

Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10B encoding while retaining the benefits of an encoding scheme. The TX Gearbox provides support for 64B/66B and 64B/67B header and payload combining. The

Interlaken interface protocol specification uses the 64B/67B encoding scheme. Refer to the Interlaken specification for further information. The Interlaken specification can be downloaded . The TX Gearbox only supports 2-byte and 4-byte interfaces. A 1-byte interface is not supported.

Scrambling of the data is done in the FPGA logic. The RocketIO? GTX Transceiver Wizard has example code for the scrambler.

Ports and Attributes

Table6-6 defines the TX Gearbox ports.

Table 6-6:

TX Gearbox PortsPort

DirectionClock Domain

Description

Output indicating how data is applied to TX Gearbox.

TXGEARBOXREADY0TXGEARBOXREADY1

0: No data can be applied

Out

TXUSRCLK2

1: Data must be applied

Use with attributes GEARBOX_ENCDEC_0 and GEARBOX_ENCDEC_1.Input for header bits.

TXHEADER0[2:0]TXHEADER1[2:0]

Bit[2]: Indicates data inverted for 64B/67B encoding

In

TXUSRCLK2

Bit[1:0]: The encoding for these bits is:01: Data header10: Control header

TXSEQUENCE0[6:0]TXSEQUENCE1[6:0]TXSTARTSEQ0TXSTARTSEQ1

InIn

TXUSRCLK2TXUSRCLK2

Input from 7-bit/6-bit counter in FPGA logic to the TX Gearbox. Time to data for 64B/67B and 64B/66B.

Input to TX Gearbox indicating the first character in the data sequence for 64B/67B and 64B/66B encoding.

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UG198 (v3.0) October 30, 2009

TX Gearbox

Internal Sequence Counter Operating Mode

As shown in Figure6-15, the internal sequence counter operating mode uses the

TXSTARTSEQ input and the TXGEARBOXREADY output in addition to the TXDATA data inputs and the TXHEADER header inputs. In this use model, the TXSEQUENCE inputs are not used. The use model is similar to the previous use model except that the TXGEARBOXREADY output is not used.

X-Ref Target - Figure 6-15Design in FPGA LogicTXDATA [15:0] or TXDATA [31:0]TX Gearbox(in GTX Transceiver)TXHEADER [2:0]Data SourceTXSTARTSEQTXGEARBOXREADYUG198_c6_15_101207RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

Chapter 6:GTX Transmitter (TX)

Table6-10 defines the TX buffering and phase-alignment attributes.

Table 6-10:

TX Buffering and Phase-Alignment Attributes

Type

Description

This shared attribute activates the built-in 5x digital oversampling circuits in both GTX_DUAL transceivers. Oversampling is supported between 1/10th of the lower border of the shared PMA PLL operating range and 4/10th of the upper border of the shared PMA PLL operating range. For data rates that need a PLL clock without oversampling that is below one-half of the lower border of the shared PMA PLL, oversampling is mandatory to ensure that the shared PMA PLL operates in its frequency range.

TRUE: Built-in 5x digital oversampling enabled for both GTX transceivers on the tile

FALSE: Digital oversampling disabled

See “Oversampling,” page 185 for more details about 5x digital oversampling.

PLL_TXDIVSEL_OUT_0PLL_TXDIVSEL_OUT_1PMA_TX_CFG_0PMA_TX_CFG_1TX_BUFFER_USE_0TX_BUFFER_USE_1

Divides the PLL clock to produce a high-speed TX clock. Because both edges of the clock are used, the divided clock must run at one-half the desired TX line rate. Available divider settings are 1, 2, and 4. Each GTX transceiver has a separate PLL_TXDIVSEL_OUT. See “Parallel In to Serial Out,” page 149.TX channel specific settings. The default value is 20'h80082.This attribute must be set to TRUE when the TX buffer is used.

Boolean

TRUE: Use the TX buffer.

FALSE: Bypass the TX buffer. The phase-alignment circuit must be used when TX_BUFFER_USE is FALSE.(1)

Selects the clock used to drive the clock domain in the PCS following the TX buffer. When using the TX buffer, this attribute is set to TXOUT.

String

The attribute must be set as follows:

TXOUT: Use when TX_BUFFER_USE = TRUETXUSR: Use when TX_BUFFER_USE = FALSE(1)

Controls inverters that optimize the clock paths within the GTX transceiver for different modes of operation. When using the TX buffer, this attribute must be set to 3'b011.

The attribute must be set as follows:

011: Use when TX_BUFFER_USE=TRUE111: Use when TX_BUFFER_USE=FALSE(1)

Notes:

1.Bypassing the TX buffer is an advanced feature and is not recommended for normal operation. TX buffer bypass operation can beguaranteed only under certain system-level conditions and data rates.

Attribute

OVERSAMPLE_MODEBoolean

Integer

20-bit Hex

TX_XCLK_SEL0TX_XCLK_SEL1

TXRX_INVERT0TXRX_INVERT1

3-bit Binary

Description

Using the TX Buffer

To use the TX buffer to resolve phase differences between the domains, TX_BUFFER_USE must be set to TRUE. The buffer should be reset whenever TXBUFSTATUS indicates an overflow or an underflow. The buffer can be reset using GTXRESET (see “Reset,” page 101)

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

TX Buffering, Phase Alignment, and TX Skew Reduction

or TXRESET (see “FPGA TX Interface,” page 120). Assertion of GTXRESET triggers a sequence that resets the entire GTX_DUAL tile.

Using the TX Phase-Alignment Circuit to Minimize TX Skew

To use the phase-alignment circuit to force the XCLK phase of multiple lanes to match the common TXUSRCLK phase, follow these steps.Initial conditions when TX_BUFFER_USE is TRUE:

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Set TX_BUFFER_USE_0 and TX_BUFFER_USE_1 to TRUE.Set TXRX_INVERT0 and TXRX_INVERT1 to 011.Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXOUT.Set PMA_TX_CFG0 and PMA_TX_CFG1 to 20'h80082.

1.2.

Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXUSR.

Wait for all clocks to stabilize, then drive TXENPMAPHASEALIGN High.

Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must berepeated. Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.

3.4.

Wait 32 TXUSRCLK2 clock cycles, and then drive TXPMASETPHASE High.Wait the number of required TXUSRCLK2 clock cycles as specified in Table6-11, andthen drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned withTXUSRCLK.

Set TX_XCLK_SEL0 and TX_XCLK_SEL1 back to TXOUT.

Assert and deassert TXRESET synchronously to TXUSRCLK. In this use mode,TXRESET must be deasserted simultaneously to all GTX Transceivers on which thedeskew operation is being performed.

Number of Required TXUSRCLK2 Clock Cycles

TXUSRCLK2 Wait Cycles

8,19216,38432,767

PLL_DIVSEL_OUT_0PLL_DIVSEL_OUT_1

124

5.6.

Table 6-11:

The phase-alignment procedure must be redone if any of the following conditions occur:???

GTXRESET is asserted

PLLPOWERDOWN is deassertedThe clocking source changed

Figure6-20 shows the TX phase-alignment procedure. TXENPMAPHASEALIGN(0/1) and TXPMASETPHASE(0/1) are independent for each GTX transceiver. This

implementation is different from the GTP_DUAL tile where TXENPHASEALIGN and TXPMASETPHASE are shared tile pins. The procedure is always applied to each GTX transceiver’s TXENPMAPHASEALIGN(0/1) signal on the tile. TXOUTCLK cannot be the source for TXUSRCLK when the TX phase-alignment circuit is used. See “FPGA TX Interface,” page 120 for details.

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009