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我的Verilog学习笔记..

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clkcnt<=16'b0000_0000_0000_0000; else begin if(clkcnt==16'b1111_1111_0101_0000) //if(clkcnt==16'b1001_1100_0100_0000) //if(clkcnt==16'b1001_1000_0100_0000) clkcnt<=16'b0000_0000_0000_0000; else clkcnt<=clkcnt+1; end end

wire tc_clkcnt;

assign tc_clkcnt=(clkcnt==16'b1111_1111_0101_0000)?1:0; //100000? //assign

tc_clkcnt=(clkcnt==16'b1001_1100_0100_0000)?1:0; //80000分频 //assign tc_clkcnt=(clkcnt==16'b1001_1000_0100_0000)?1:0;

//对tc_clkcnt二分频 reg clkdiv;

always @ (posedge tc_clkcnt) if(!rst) clkdiv<=0; else clkdiv<=~clkdiv;

//对clkdiv二分频 reg clk_int; always @ (posedge clkdiv) if(rst==0) clk_int<=0; else clk_int<=~clk_int; always @ (negedge clkdiv) if(rst==0) lcd_en<=0; else lcd_en<=~lcd_en; //为满足总线时序而进行的两次二分频,在rs,rw,io里孟跳沿触?

//有限状态机 //reg [15:0] myclkcnt; //reg myclk; always @ (posedge clk_int or negedge rst) if(!rst) begin

n,所以这

stage<=START;

ddram_address<=8'h80; shift_flag<=1; shift_freq<=8'h00;

//ddram_address<=8'b1001_0000; //写DDRAM缓冲区 shift_count<=5'b0_0000; //myclkcnt<=16'h0000; flag<=0; //flag1<=1; end else begin case(stage) START :begin lcd_data<=8'bzzzz_zzzz; stage<=SETFUNCTION; end STOP :begin stage<=STOP; end CLEAR_SCREEN :begin //0000_0001 01H lcd_rs<=0; lcd_rw<=0; lcd_data<=8'b0000_0001; stage<=SETMODE; end SETMODE :begin //0000_0110 06H lcd_rs<=0; lcd_rw<=0; lcd_data[7:2]<=6'b000001; lcd_data[1]<=CURSOR_MOVE_RIGHT; lcd_data[0]<=WORD_NOSHIFT; stage<=DISPLAY_CTRL_ON; end CURSOR_BACK :begin //0000_0010 02H lcd_rs<=0; lcd_rw<=0; lcd_data<=8'b00000010; stage<=SETDDRAM; end DISPLAY_CTRL_OFF:begin //0000_1010 08H lcd_rs<=0; lcd_rw<=0; lcd_data[7:3]<=5'b00001;

lcd_data[2]<=DISPLAY_OFF; lcd_data[1]<=CURSOR_OFF; lcd_data[0]<=CURSOR_FLASH_OFF; stage<=CLEAR_SCREEN; end DISPLAY_CTRL_ON:begin //0000_1100 0CH lcd_rs<=0; lcd_rw<=0; lcd_data[7:3]<=5'b00001; lcd_data[2]<=DISPLAY_ON; lcd_data[1]<=CURSOR_ON; lcd_data[0]<=CURSOR_FLASH_ON; stage<=SETDDRAM; end SETFUNCTION :begin //0011_1000 38H lcd_rs<=0; lcd_rw<=0; lcd_data[7:5]<=3'b001; lcd_data[4]<=DATAWIDTH8; lcd_data[3]<=TWOLINE_DISPLAY; lcd_data[2]<=FONT5x7; lcd_data[1:0]<=2'b00; stage<=SETFUNCTION2; end SETFUNCTION2 :begin //0011_1000 38H lcd_rs<=0; lcd_rw<=0; lcd_data[7:5]<=3'b001; lcd_data[4]<=DATAWIDTH8; lcd_data[3]<=TWOLINE_DISPLAY; lcd_data[2]<=FONT5x7; lcd_data[1:0]<=2'b00; stage<=DISPLAY_CTRL_OFF; end // SETCGRAM :begin

lcd_rs<=0;lcd_rw<=0;data<=8'b01000000;state<=START;end SETDDRAM :begin //1XXX_XXXX lcd_rs<=0; lcd_rw<=0; lcd_data[7:0]<=ddram_address; stage<=WRITE_RAM; end // SETDDRAM1 :begin

lcd_rs<=0;lcd_rw<=0;data<=8'b11000000;state<=WRITERAM;end //设置第二行首地址

WRITE_RAM

:begin //XXXX_XXXX

//M 的行号,0为第一行,1为第二行

if(ddram_address<=8'h8F) //if(ddram_address<=8'h9F) begin

lcd_rs<=1; //写数据 lcd_rw<=0;

//data<=ddram(address);

case(ddram_address) 8'h80:lcd_data<=8'h43;

//C 8'h81:lcd_data<=8'h68; //h 8'h82:lcd_data<=8'h61; //a 8'h83:lcd_data<=8'h6e; //n 8'h84:lcd_data<=8'h67; //g 8'h85:lcd_data<=8'h73; //s 8'h86:lcd_data<=8'h68; //h 8'h87:lcd_data<=8'h61;

//a

8'h88:lcd_data<=8'h4d;

8'h89:lcd_data<=8'h69; //i 8'h8A:lcd_data<=8'h6e; //n 8'h8B:lcd_data<=8'h67; //g 8'h8C:lcd_data<=8'h77; //w 8'h8D:lcd_data<=8'h65; //e 8'h8E:lcd_data<=8'h69; //i 8'h8F:lcd_data<=8'h21; //! default:lcd_data<=8'h20; endcase ddram_address<=ddram_address+1; //stage<=WRITE_RAM; end else begin if (flag==0) begin ddram_address<=8'hC0; flag<=1; //flga指明当前操作 //lcd_data<=8'h20; lcd_rs<=1; lcd_rw<=1; //屏蔽下次输入 stage<=SETDDRAM;

end

8'hC0:lcd_data<=8'h44; //D 8'hC1:lcd_data<=8'h65; //e 8'hC2:lcd_data<=8'h73; //s 8'hC3:lcd_data<=8'h69; //i 8'hC4:lcd_data<=8'h67; //g 8'hC5:lcd_data<=8'h6e; //n 8'hC6:lcd_data<=8'h62; //b 8'hC7:lcd_data<=8'h79; //y 8'hC8:lcd_data<=8'h3a; //: 8'hC9:lcd_data<=8'h53; //S 8'hCA:lcd_data<=8'h68; //h 8'hCB:lcd_data<=8'h75; //u 8'hCC:lcd_data<=8'h77; //w 8'hCD:lcd_data<=8'h61; //a 8'hCE:lcd_data<=8'h6e; //n 8'hCF:lcd_data<=8'h67; //g default:lcd_data<=8'h20;

ddram_address<=ddram_address+1;

else begin if(ddram_address<=8'hCF) //if (ddram_address<=8'hDF) begin lcd_rs<=1; lcd_rw<=0;

case(ddram_address)

endcase

//stage<=WRITE_RAM; end else begin stage<=SHIFT; //stage<=STOP; lcd_rs<=1; lcd_rw<=1; //shift_flag<=0; //lcd_data<=8'h00; end

end

我的Verilog学习笔记..

clkcnt<=16'b0000_0000_0000_0000;elsebeginif(clkcnt==16'b1111_1111_0101_0000)//if(clkcnt==16'b1001_1100_0100_0000)//if(clkcnt==16'b1001_1000_0100_0000)clkcnt<
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