Ordering Information
Figure1–1 shows the ordering codes for StratixIII devices.
f
For more information about a specific package, refer to the StratixIII Device Package Information chapter.
Figure1–1.StratixIII Device Packaging Ordering Information
EP3SLFamily S i g n a t u r eEP3SL:Stratix III LogicEP3SE:Stratix III DSP/Memory150F1152C2ESOptional SuffixIndicates specific device options ES: Engineering sample N:Lead-free devicesL: Low-voltage devicesSpeed Grade507080110150200260340Package TypeF:FineLine BGA (FBGA)
H:Hybrid FineLine BGA (HBGA)
Pi n CountNumber of pins for a particular package:484780115215171760
2, 3, or 4, with 2 being the fastestDevice TypeOperating TemperatureC:Commercial temperature (tJ = 0 C to 85 C)I:Industrial temperature (tJ = -40 C to 100 C)
Chapter Revision History
Table1–6 lists the revision history for this chapter.
Table1–6.Chapter Revision History(Part 1 of 2)
DateMarch 2010May 2009February 2009Version1.81.71.6Updated Table1–2.Updated “I/O Banks and I/O Structure” section.Updated “Features” section.Updated Table1–1.Removed “Referenced Documents” section.Updated “Features” section.Updated Table1–1 and Table1–5.Updated New Document Format.Changes MadeUpdated for the QuartusII software version 9.1 SP2 release:■■Updated “Software” and “Signal Integrity” sections.■■■■October 20081.5■■Stratix III Device Handbook, Volume 1
Figure8–20.StratixIII IOE Input Registers(Note1)
DQDDR Input RegistersDQDFFInput Reg AIDQneg_reg_outDQDifferentialDFFDFFdirectinDQS/CQ (3), (9)Input Input Reg BAlignment & Synchronization Registers Half Data Rate Registers0BufferIInput Reg CI0DQ1CQn DQSn (9) (4)0datain [0]DQDQ10To Core 1DQ1dataoutdataout[2] (7)DFFDFFDFFDQTo CoreDFF dataout [0]delayctrlinDFFdataoutbypassDQDQ(7)enaphasetransferreg(8)6phasectrlinenainputcycledelay4
OCT
StratixIII devices feature dynamic calibrated OCT, in which series termination (OCT RS) is turned on when driving signals and turned off when receiving signals, while the parallel termination (OCT RT) is turned off when driving signals and turned on when receiving signals. This feature complements the DDR3/DDR2 SDRAM on-die
termination (ODT), whereby memory termination is turned off when the memory is sending data and turned on when receiving data. You can also use OCT for other memory interfaces to improve signal integrity.1
You cannot use the programmable drive strength and programmable slew rate features when using OCT RS.
To use dynamic calibrated OCT, you must use the RUP and RDN pins to calibrate the OCT calibration block. You can use one OCT calibration block to calibrate one type of termination with the same VCCIO on the entire device. There are up to ten OCT
calibration blocks to allow for different types of terminations throughout the device. For more information, refer to “Dynamic OCT Control” on page8–33.1
You have the option to use the OCT RS feature with or without calibration. However, the OCT RT feature is only available with calibration.
You can also use the RUP and RDN pins as DQ pins. However, you cannot use the ×4 DQS/DQ groups where the RUP and RDN pins are located if you are planning to use dynamic calibrated OCT. The RUP and RDN pins are located in the first and last ×4 DQS/DQ group on each side of the device.
Use the OCT RT/RS setting for uni-directional read and write data; use a dynamic OCT setting for bi-directional data signals.
Programmable IOE Delay Chains
You can use programmable delay chains in the StratixIII I/O registers as deskewing circuitry. Each pin can have a different input delay from the pin to input register or a delay from the output register to the output pin to ensure that the bus has the same delay going into or out of the FPGA. This feature helps read and write time margins as it minimizes the uncertainties between signals in the bus. 1
Deskewing circuitry and programmable IOE delay chains are the same circuit.
Programmable Output Buffer Delay
In addition to allowing output buffer duty cycle adjustment, the programmable output buffer delay chain allows you to adjust the delays between data bits in your output bus to introduce or compensate channel-to-channel skew. Incorporating skew to the output bus helps to minimize simultaneous switching events by enabling smaller parts of the bus to switch simultaneously, instead of the whole bus. This feature is particularly useful in DDR3 SDRAM interfaces where the memory system clock delay can be much larger than the data and data clock/strobe delay. Use this delay chain to add delay to the data and data clock/strobe to better match the memory system clock delay.
Stratix III Device Handbook, Volume 1
Chapter 8:External Memory Interfaces in StratixIII Devices
StratixIII External Memory Interface Features
Stratix III Device Handbook, Volume 1
Chapter 8:External Memory Interfaces in StratixIII DevicesChapter Revision History
Chapter Revision History
Table8–13 lists the revision history for this chapter.
Table8–13.Chapter Revision History(Part 1 of 2)Date and Revision■■Changes MadeAdded “Delay Chain” section.Updated “DLL”, “DQS Logic Block”, and “Dynamic OCT Control”sections.Added Figure8–22, Figure8–23, Figure8–24, and Figure8–25.Updated Figure8–12, Figure8–13,and Figure8–20.Added Table8–11 and Table8–12.Updated Table8–7.Minor text edits.Updated Table8–1, Table8–2, Table8–3, Table8–2, Table8–4, andTable8–10.Updated Figure8–3, Figure8–4, Figure8–5, Figure8–6, and Figure8–7.Updated “DLL”, “Memory Interfaces Pin Support”, and “Rules toCombine Groups”sections.Updated Table8–1,Table8–2, and Table8–6.Updated “Data and Data-Strobe/Clock Pins” section.Removed “Referenced Document” section.Updated Table8–1, Table8–2, Table8–3, Table8–4, Table8–5,Table8–7, and Table8–8.Updated the “Rules to Combine Groups”, “Phase Offset Control”, “OCT”,“Introduction”, “Memory Interfaces Pin Support”, “Combining ×16/×18DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface”, “Rules toCombine Groups”, “DQS Phase-Shift Circuitry”, “DLL”, and “DQS DelayChain” sections.Updated Figure8–2, Figure8–4, Figure8–10, Figure8–21, andFigure8–22.Updated New Document Format.Added (Note3) to Table8–5.Summary of ChangesMarch 2010, version 1.9■■■■■■Updated for the QuartusII software version 9.1 SP2 release.May 2009, version 1.8■■—February 2009,version 1.7■■■■—■October 2008, version 1.6■—■■July 2008, version 1.5Updated Table8–1 and Table8–2.■—Updated Figure8–2, Figure8–9, Figure8–18, Figure8–21, andFigure8–22.Updated Table8–1, Table8–2, Table8–3, Table8–4, Table8–7, andTable8–10.Added Table8–7 and Table8–8.Added Figure8–19.Added new “Supporting ×36 QDR II+/QDR II SRAM Interfaces in the F780 and F1152-Pin Packages” section.Updated “Data and Data Clock/Strobe Pins”.Updated “Referenced Documents”.Text, Table, and Figure updates.■May 2008, version 1.4■■■■■Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP4SGX290KF40C2N中文规格书 - 图文
