3.Intel Agilex I/O Termination
UG-20214 | 2021.04.05
Steps to assign OCT features to your pins:1.2.3.4.5.
In the Intel Quartus Prime click Assignments ? Assignment Editor.In the To column, search for the pin that you want to configure.
In the Assignment Name column, select the desired termination feature basedon the assignment names listed in Table 31 on page 55.In the Value column, select the desired termination value.Click save to save your changes.
3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation
The OCT Intel FPGA IP allows you to dynamically calibrate I/O with reference to anexternal resistor. The OCT IP improves signal integrity, reduces board space, and isnecessary for communicating with external devices such as memory interfaces.The OCT IP supports the following features:?????
Support for up to 12 on-chip termination (OCT) blocks
Support for calibrated on-chip series termination (RS) and calibrated on-chipparallel termination (RT) on all I/O pins
Support dynamically switching between series termination (RS) and paralleltermination (RT)
Support for OCT calibration in power-up and user modesSupport double calibration for DDR4 and non-DDR4 applications
3.1.4.2.1. Release Information
Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versionsuntil v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, IntelFPGA IP has a new versioning scheme.
The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Primesoftware version. A change in:???
Table 32.
X indicates a major revision of the IP. If you update the Intel Quartus Primesoftware, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.
Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.
OCT Intel FPGA IP Release Information
Item
Description
19.3.021.12021.03.29
IP Version
Intel Quartus Prime VersionRelease Date
Related Information
OCT Intel FPGA IP Release Notes
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3.Intel Agilex I/O TerminationUG-20214 | 2021.04.05
3.1.4.2.2. OCT Intel FPGA IP Quick Start Guide
Generating the OCT Intel FPGA IP (Intel Quartus Prime Pro Edition)
Double-click the OCT Intel FPGA IP in the IP Catalog to launch the parameter editor.The parameter editor allows you to define a custom variation of the IP. The parametereditor generates the IP variation synthesis and optional simulation files, and addsthe .ip file representing the variation to your project automatically.
Follow these steps to locate, instantiate, and customize the IP in the parameter editor:1.2.3.
Create or open an Intel Quartus Prime project (.qpf) to contain the instantiatedIP variation.
In the IP Catalog (Tools ? IP Catalog), locate and double-click the OCT IntelFPGA IP to customize.
Specify a top-level name for your custom IP variation. Do not include spaces in IPvariation names or paths. The parameter editor saves the IP variation settings in afile named
Figure 37.OCT Intel FPGA IP Parameter Editor
4.
Set the parameter values in the parameter editor and view the block diagram forthe component. The Parameterization Messages tab at the bottom displays anyerrors in IP parameters.
Click Generate HDL. The Generation dialog box appears.
Specify output file generation options, and then click Generate. The synthesis andsimulation files generate according to your specifications.
To generate a simulation testbench, click Generate ? Generate TestbenchSystem. Specify testbench generation options, and then click Generate.To generate an HDL instantiation template that you can copy and paste into yourtext editor, click Generate ? Show Instantiation Template.
Click Finish. Click Yes if prompted to add files representing the IP variation toyour project.
5.6.7.8.9.
10.After generating and instantiating your IP variation, make appropriate pin
assignments to connect ports.
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FPGA可编程逻辑器件芯片EP3C120F484C7N中文规格书
