基于FPGA的可控ARM异常表设计实现
黄丽霞;李俊红;刘立国;柳香
【期刊名称】《计算机工程与设计》 【年(卷),期】2011(032)012
【摘要】为了提高ARM处理器对异常的管理效率和异常的响应速度,在ARM中断向量表基础上,通过集成异常仲裁电路和可控制异常处理分支,提出了高效的可控ARM异常表及其实现方法.引入三级树状结构来表示可控ARM异常表和各类异常处理路径,通过改变异常处理分支实现异常表的可控制性.详细介绍了可控ARM异常表的实体定义、接口描述和实现算法.利用FPGA开发板对可控异ARM异常表进行功能仿真调试,验证了可控ARM异常表的正确性、可靠性和可控制性.%To improve the efficiency of abnormity management and the response speed of abnormity in ARM processor, a controllable abnormity table (CAT) for ARM based on the traditional interrupt vector table (IVT) for ARM and its realization are proposed. The CAT is efficiency by integrating the arbitration controller and the processing branches for abnormality into the traditional interrupt vector table. Firstly, tree structure with three levels in depth is introduced, which is used for describing CAT and every processing branch above. Then the controllability of CAT can be realized by changing the function of the branches. Secondly, entity definitions, description for ports and the algorithm for realization of CAT are proposed. Finally, the function simulation and debugging of the CAT are done on the FPGA board. And
基于FPGA的可控ARM异常表设计实现
