FPGA可编程逻辑器件芯片EP2SGX90FF1152C3中文规格书 - 图文

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SII52002-4.5

Introduction

TriMatrix Memory Overview

2.TriMatrix EmbeddedMemory Blocks in StratixIIand StratixIIGX Devices

Stratix?II and StratixIIGX devices feature the TriMatrix? memory structure, consisting of three sizes of embedded RAM blocks that efficiently address the memory needs of FPGA designs.

TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, which are each configurable to support manyfeatures. TriMatrix memory provides up to 9megabits of RAM at up to550 MHz operation, and up to 16 terabits per second of total memorybandwidth per device. This chapter describes TriMatrix memory blocks,modes, and features.

The TriMatrix architecture provides complex memory functions for different applications in FPGA designs. For example, M512 blocks are used for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical; M4K blocks are ideal for

applications requiring medium-sized memory, such as asynchronous transfer mode (ATM) cell processing; and M-RAM blocks are suitable for large buffering applications, such as internet protocol (IP) packet buffering and system cache.

The TriMatrix memory blocks support various memory configurations, including single-port, simple dual-port, true dual-port (also known as bidirectional dual-port), shift register, and read-only memory (ROM) modes. The TriMatrix memory architecture also includes advanced

features and capabilities, such as parity-bit support, byte enable support, pack mode support, address clock enable support, mixed port width support, and mixed clock mode support.

When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.

TriMatrix Embedded Memory Blocks in StratixII and StratixIIGX Devices

Figure2–3.StratixII and Stratix II GX Address Clock Enable During Read Cycle Waveform

inclockrdaddressrdenaddressstalllatched address(inside memory)ana0doutndout0dout0dout1a1dout1dout1dout1dout1a4dout1dout4a5dout4dout5a0a1a2a3a4a5a6q (synch)doutn-1q (asynch)doutnFigure2–4.StratixII and Stratix II GX Address Clock Enable During Write Cycle Waveform

inclockwraddressdatawrenaddressstalllatched address(inside memory)contents at a0contents at a1contents at a2contents at a3contents at a4contents at a5XXXXanXXXX0102XXXX0405a0a10003a4a5a000a101a202a303a404a505a606Memory Modes

StratixII and StratixIIGX TriMatrix memory blocks include input

registers that synchronize writes, and output registers to pipeline data to improve system performance. All TriMatrix memory blocks are fully synchronous, meaning that all inputs are registered, but outputs can be either registered or unregistered.

Stratix II Device Handbook, Volume 2

Read-During-Write Operation at the Same Address

Stratix II Device Handbook, Volume 2

TriMatrix Embedded Memory Blocks in StratixII and StratixIIGX Devices

Stratix II Device Handbook, Volume 2

Referenced Documents

This chapter references the following documents:

■■■■■■■

AN 207: TriMatrix Memory Selection Using the QuartusII SoftwareAN 210: Converting Memory from Asynchronous to Synchronous forStratix and StratixGX Designs

FIFO Partitioner Megafunction User Guide

Single- and Dual-Clock FIFO Megafunctions User Guide

StratixII Device Family Data Sheet (volume1) of the StratixII DeviceHandbook

StratixIIGX Device Family Data Sheet (volume1) of the StratixIIGXDevice Handbook

Using Parity to Detect Memory Errors white paper

Document

Revision History

Table2–15 shows the revision history for this chapter.

Table2–15.Document Revision History Date and Document Version

Changes Made

Summary of Changes

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