DS099 (v3.1) June 27, 2013Product Specification
Introduction
The Spartan?-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table1.
The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex?-II platform technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Table 1:Summary of Spartan-3 FPGA Attributes
DeviceXC3S50(2)XC3S200(2)XC3S400(2)XC3S1000(2)XC3S1500XC3S2000XC3S4000XC3S5000
CLB Array
(One CLB = Four Slices)System Equivalent
GatesLogic Cells(1)Total
RowsColumns
CLBs 50K200K400K1M1.5M2M4M5M
1,7284,3208,06417,28029,95246,08062,20874,880
16243248648096104
1220284052647280
1924808961,9203,3285,1206,9128,320
Features
??
Low-cost, high-performance logic solution for high-volume,consumer-oriented applications?Densities up to 74,880 logic cellsSelectIO? interface signaling?Up to 633 I/O pins?622+ Mb/s data transfer rate per I/O?18 single-ended signal standards?8 differential I/O standards including LVDS, RSDS?Termination by Digitally Controlled Impedance?Signal swing ranging from 1.14V to 3.465V?Double Data Rate (DDR) support?DDR, DDR2 SDRAM support up to 333Mb/sLogic resources?Abundant logic cells with shift register capability?Wide, fast multiplexers?Fast look-ahead carry logic?Dedicated 18 x 18 multipliers?JTAG logic compatible with IEEE 1149.1/1532SelectRAM? hierarchical memory?Up to 1,872 Kbits of total block RAM?Up to 520 Kbits of total distributed RAMDigital Clock Manager (up to four DCMs)?Clock skew elimination?Frequency synthesis?High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE? and WebPACK? softwaredevelopment systems
MicroBlaze? and PicoBlaze? processor, PCI?,PCIExpress? PIPE Endpoint, and other IP coresPb-free packaging options
Automotive Spartan-3 XA Family variant
?
??
?????
Distributed Block
Dedicated
RAM Bits RAM Bits DCMs
Multipliers
(K=1024)(K=1024)
12K30K56K120K208K320K432K520K
72K216K288K432K576K720K1,728K1,872K
4121624324096104
24444444
Maximum
Max.
Differential
User I/O
I/O Pairs124173264391487565633633
5676116175221270300300
Notes:
1.2.Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. \otal CLBs\These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 46:Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5Max(3)
Synchronous Output Enable/Disable TimesTIOCKHZ
Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data
LVCMOS25, 12mA output drive, Fast slew rate
All
0.74
0.85
ns
-4Max(3)
Units
TIOCKON(2)
All0.720.82ns
Asynchronous Output Enable/Disable TimesTGTS
Time from asserting the Global Three State LVCMOS25, 12mA (GTS) net to when the Output pin enters the output drive, Fast slew high-impedance staterate
XC3S200
XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
7.718.38
8.879.63
nsns
Set/Reset TimesTIOSRHZ
Time from asserting TFF’s SR input to when LVCMOS25, 12mA
output drive, Fast slew the Output pin enters a high-impedance
ratestate
Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data
All
1.55
1.78
ns
TIOSRON(2)
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
2.242.91
2.573.34
nsns
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.
Table 47:Output Timing Adjustments for IOB
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
Speed Grade
-4
Units
Single-Ended StandardsGTLGTL_DCIGTLPGTLP_DCIHSLVDCI_15HSLVDCI_18
00.130.030.231.510.81
0.020.150.040.271.740.94
nsnsnsnsnsns
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47:Output Timing Adjustments for IOB (Cont’d)
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
LVCMOS33
Slow
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
Fast
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
LVDCI_33LVDCI_DV2_33LVTTL
Slow
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
Fast
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
6.384.834.013.922.912.812.493.861.870.620.610.160.140.060.280.267.274.943.983.982.972.842.654.321.871.271.190.420.270.16
Speed Grade
-47.345.554.614.513.353.232.864.442.150.710.700.190.160.070.320.308.365.694.584.583.423.263.044.972.151.471.370.480.320.18
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsUnits
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47:Output Timing Adjustments for IOB (Cont’d)
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
PCI33_3SSTL18_ISSTL18_I_DCISSTL18_IISSTL2_ISSTL2_I_DCISSTL2_IISSTL2_II_DCI
0.740.070.220.300.230.190.130.10
Speed Grade
-40.850.070.250.340.260.220.150.11
nsnsnsnsnsnsnsnsUnits
Differential StandardsLDT_25 (ULVDS_25)LVDS_25BLVDS_25LVDSEXT_25LVPECL_25RSDS_25DIFF_HSTL_II_18DIFF_HSTL_II_18_DCIDIFF_SSTL2_IIDIFF_SSTL2_II_DCI
–0.06–0.090.02–0.150.160.05–0.020.750.130.10
–0.05–0.070.04–0.130.180.06–0.010.860.150.11
nsnsnsnsnsnsnsnsnsns
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 48:Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard(IOSTANDARD)DIFF_SSTL2_IIDIFF_SSTL2_II_DCINotes:
1.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching thresholdVICM – The common mode input voltage
VM – Voltage of measurement point on signal transitionVL – Low-level test voltage at Input pinVH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1MW when no parallel termination is requiredVT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.According to the PCI specification.
Inputs
VREF (V)
-
Outputs
VH (V)VICM + 0.75
Inputs and Outputs
VT (V)1.25
VL (V)VICM – 0.75
RT (Ω)50
VM (V) VICM
2.3.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load Conditions in Application
IBIS Models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 48, VT, RT, and VM. Do not confuse VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth
parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link.
Simulate delays for a given application according to its specific load conditions as follows:
1.Simulate the desired signal standard with the output driver connected to the test setup shown in Figure35. Use
parameter values VT, RT, and VM from Table48. CREF is zero.2.Record the time to VM.
3.Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load.4.Record the time to VMEAS.
5.Compare the results of steps 2 and 4. The increase (or decrease) in delay should be added to (or subtracted from) the
appropriate Output standard adjustment (Table47) to yield the worst-case delay of the PCB trace.
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC6VLX75T-1FF784C中文规格书 - 图文
