DS099 (v3.1) June 27, 2013Product Specification
Introduction
This data sheet module describes the various pins on a Spartan?-3 FPGA and how they connect to the supported component packages.?????
The Pin Types section categorizes all of the FPGA pins by their function type.The Pin Definitions section provides a top-level description for each pin on the device.
The Detailed, Functional Pin Descriptions section offers significantly more detail about each pin, especially for the dual- or special-function pins used during device configuration.
Some pins have associated behavior that is controlled by settings in the configuration bitstream. These options aredescribed in the Bitstream Options section.
The Package Overview section describes the various packaging options available for Spartan-3 FPGAs. Detailed pinlist tables and footprint diagrams are provided for each package solution.
Pin Descriptions
Pin Types
A majority of the pins on a Spartan-3 FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3 device packages, as outlined in Table69. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table.Table 69:Types of Pins on Spartan-3 FPGAs
Pin Type/ Color Code
I/ODUAL
Description
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os.
Dual-purpose pin used in some configuration modes during the configuration
process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. There are 12
dual-purpose configuration pins on every package. The INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM during configuration.
IO,
IO_Lxxy_#
Pin Name
IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1, IO_Lxxy_#/D2, IO_Lxxy_#/D3, IO_Lxxy_#/D4, IO_Lxxy_#/D5, IO_Lxxy_#/D6, IO_Lxxy_#/D7, IO_Lxxy_#/CS_B, IO_Lxxy_#/RDWR_B, IO_Lxxy_#/BUSY/DOUT, IO_Lxxy_#/INIT_B
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has CCLK, DONE, M2, M1, M0, seven dedicated configuration pins. These pins are powered by VCCAUX and have PROG_B, HSWAP_ENa dedicated internal pull-up resistor to VCCAUX during configuration.
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four TDI, TMS, TCK, TDOdedicated JTAG pins. These pins are powered by VCCAUX and have a dedicated internal pull-up resistor to VCCAUX during configuration.
Dual-purpose pin that is either a user-I/O pin or used to calibrate output buffer IO/VRN_#
impedance for a specific bank using Digital Controlled Impedance (DCI). There are IO_Lxxy_#/VRN_#two DCI pins per I/O bank.IO/VRP_#
IO_Lxxy_#/VRP_#
JTAG
DCI
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 61:Switching Characteristics for the DFS
Speed Grade
Symbol
Output Frequency RangesCLKOUT_FREQ_FX_LFCLKOUT_FREQ_FX_HF
Frequency for the CLKFX and CLKFX180 outputs
LowHigh
AllAll
18210
210326(2)
18210
210307(2)
MHzMHz
Description
Frequency Mode
Device
Min
-5Max
Min
-4Max
Units
Output Clock JitterCLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180 outputs
All
All
Note 3Note 3Note 3Note 3
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_FXDuty cycle precision for the CLKFX
and CLKFX180 outputs
All
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
––––––––
±100±100±250±400±400±400±400±400
––––––––
±100±100±250±400±400±400±400±400
pspspspspspspsps
Phase AlignmentCLKOUT_PHASE
Phase offset between the DFS output and the CLK0 output
All
All
–
±300
–
±300
ps
Lock TimeLOCK_DLL_FX
When using the DFS in conjunction with the DLL: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase.
When using the DFS without the DLL: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. By asserting the LOCKED signal, the DFS indicates valid CLKFX and CLKFX180 signals.
All
All
–
10.0
–
10.0
ms
LOCK_FXAllAll–10.0–10.0ms
Notes:
1.2.3.4.5.
The numbers in this table are based on the operating conditions set forth in Table32 and Table60.
Mask revisions prior to the E mask revision have a CLKOUT_FREQ_FX_HF max of 280 MHz. See Mask and Fab Revisions, page58.
Use the DCM Clocking Wizard in the ISE software for a Spartan-3 device specific number. Jitter number assumes 150ps of input clock jitter.The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
X-Ref Target - Figure 36VCCINT(Supply)VCCAUX(Supply)VCCO Bank 4(Supply)PROG_B(Input)INIT_B(Open-Drain)CCLK(Output)1.2V1.0V2.5V2.0V1.0VTPORTPROGTPLTICCKDS099-3_03_120604Notes:
1.2.3.
The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 36:Waveforms for Power-On and the Beginning of Configuration
Table 65:Power-On Timing and the Beginning of Configuration
SymbolTPOR(2)
DescriptionDevice
All Speed GradesMin––––––––0.3––––––––2500.25
Max55557777–22223333–4.0
Unitsmsmsmsmsmsmsmsmsμsmsmsmsmsmsmsmsmsnsμs
The time from the application of VCCINT, VCCAUX, and VCCO XC3S50Bank 4 supply voltage ramps (whichever occurs last) to the XC3S200rising transition of the INIT_B pin
XC3S400
XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TPROGTPL(2)
The width of the low-going pulse on the PROG_B pinThe time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin
AllXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TINITTICCK(3)
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin
AllAll
Notes:
1.2.3.
The numbers in this table are based on the operating conditions set forth in Table32. This means power must be applied to all VCCINT, VCCO,and VCCAUX lines.
Power-on reset and the clearing of configuration memory occurs during this period.This specification applies only for the Master Serial and Master Parallel modes.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 37PROG_B(Input)INIT_B(Open-Drain)TCCLCCLK(Input/Output)TDCCDIN(Input)Bit 0TCCDBit 11/FCCSERBit nBit n+1TCCODOUT(Output)Bit n-64Bit n-63DS099-3_04_071604TCCHFigure 37:Waveforms for Master and Slave Serial Configuration
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 38PROG_B(Input)INIT_B(Open-Drain)TSMCSCCCS_B(Input)TSMCCCSTSMCCWTSMWCCRDWR_B(Input)TCCHCCLK(Input/Output)TSMDCCD0 - D7(Inputs)Byte 0TSMCCDByte 1TSMCKBYBUSY(Output)High-ZBUSYDS099-3_05_041103TCCL1/FCCPARByte nTSMCKBYByte n+1High-ZFigure 38:Waveforms for Master and Slave Parallel ConfigurationTable 67:Timing for the Master and Slave Parallel Configuration Modes
Symbol
Clock-to-Output TimesTSMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin
Slave
–
12.0
ns
Description
Slave/Master
All Speed GradesMin
Max
Units
Setup TimesTSMDCCTSMCSCCTSMCCW(3)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
The time from the setup of a logic level at the CS_B pin to the rising transition at the CCLK pin
The time from the setup of a logic level at the RDWR_B pin to the rising transition at the CCLK pin
Both
10.010.010.0
–––
nsnsns
Hold TimesTSMCCDTSMCCCSTSMWCC(3)
The time from the rising transition at the CCLK pin to the point when data is last held at the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last held at the RDWR_B pin
Both
000
–––
nsnsns
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XQ4010E-4PG191M中文规格书 - 图文
