Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
X-Ref Target - Figure 36VCCINT(Supply)VCCAUX(Supply)VCCO Bank 4(Supply)PROG_B(Input)INIT_B(Open-Drain)CCLK(Output)1.2V1.0V2.5V2.0V1.0VTPORTPROGTPLTICCKDS099-3_03_120604Notes:
1.2.3.
The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 36:Waveforms for Power-On and the Beginning of Configuration
Table 65:Power-On Timing and the Beginning of Configuration
SymbolTPOR(2)
DescriptionDevice
All Speed GradesMin––––––––0.3––––––––2500.25
Max55557777–22223333–4.0
Unitsmsmsmsmsmsmsmsmsμsmsmsmsmsmsmsmsmsnsμs
The time from the application of VCCINT, VCCAUX, and VCCO XC3S50Bank 4 supply voltage ramps (whichever occurs last) to the XC3S200rising transition of the INIT_B pin
XC3S400
XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TPROGTPL(2)
The width of the low-going pulse on the PROG_B pinThe time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin
AllXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TINITTICCK(3)
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin
AllAll
Notes:
1.2.3.
The numbers in this table are based on the operating conditions set forth in Table32. This means power must be applied to all VCCINT, VCCO,and VCCAUX lines.
Power-on reset and the clearing of configuration memory occurs during this period.This specification applies only for the Master Serial and Master Parallel modes.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 37PROG_B(Input)INIT_B(Open-Drain)TCCLCCLK(Input/Output)TDCCDIN(Input)Bit 0TCCDBit 11/FCCSERBit nBit n+1TCCODOUT(Output)Bit n-64Bit n-63DS099-3_04_071604TCCHFigure 37:Waveforms for Master and Slave Serial Configuration
Table 66:Timing for the Master and Slave Serial Configuration Modes
Symbol
Clock-to-Output TimesTCCO
The time from the falling transition on the CCLK pin to data appearing at the DOUT pin
Both
1.5
12.0
ns
Description
Slave/Master
All Speed GradesMin
Max
Units
Setup TimesTDCC
The time from the setup of data at the DIN pin to the rising transition at the CCLK pin
Both
10.0
–
ns
Hold TimesTCCD
The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin
Both
0
–
ns
Clock TimingTCCHTCCLFCCSER
CCLK input pin High pulse width CCLK input pin Low pulse widthFrequency of the clock signal at the CCLK input pin
No bitstream compressionWith bitstream compressionDuring STARTUP phase
ΔFCCSERNotes:
1.2.
The numbers in this table are based on the operating conditions set forth in Table32.
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
Slave5.05.0000
∞∞66(2)2050+50%
nsnsMHzMHzMHz–
Variation from the CCLK output frequency set using the ConfigRate BitGen option
Master–50%
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2V6000-6BG575C中文规格书
