FPGA可编程逻辑器件芯片EP1S30F1020I5N中文规格书 - 图文

C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross

M-RAM blocks and also drive to row and column interconnects at everyfourth LAB. C16 interconnects drive LAB local interconnects via C4 andR4 interconnects and do not drive LAB local interconnects directly.All embedded blocks communicate with the logic array similar to LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0].Table2–2 shows the StratixII device’s routing scheme.

Table2–2. StratixII Device Routing Scheme(Part 1 of2)

Destination

Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksShared arithmetic chainCarry chainRegister chainLocal interconnectDirect link interconnectR4 interconnectR24 interconnectC4 interconnectC16 interconnectALM

M512 RAM blockM4K RAM blockM-RAM blockDSP blocks

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Stratix II Device Handbook, Volume 1

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ALMSource

Row IOETriMatrix Memory

Table2–2. StratixII Device Routing Scheme(Part 2 of2)

Destination

Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksColumn IOERow IOE

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TriMatrix Memory

TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table2–3 shows the size and features of the different RAM blocks.

Table2–3.TriMatrix Memory Features(Part 1 of2)

Memory Feature

Maximum performance True dual-port memorySimple dual-port memorySingle-port memoryShift registerROMFIFO bufferPack modeByte enable

Address clock enableParity bitsMixed clock modeMemory initialization (.mif)

M512 RAM Block (32×18 Bits)

500 MHz

M4K RAM Block (128×36 Bits)

550 MHz

ALMSource

M-RAM Block(4K×144Bits)

420 MHz

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Stratix II Device Handbook, Volume 1

Row IOEStratixII Architecture

Stratix II Device Handbook, Volume 1

StratixII Architecture

The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure2–21.

The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can

communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure2–22 shows the M4K RAM block to logic array interface.

Figure2–21.M4K RAM Block Control Signals

DedicatedRow LABClocksLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnect6clock_bclock_aclocken_aclocken_brenwe_arenwe_baclr_aaclr_bStratix II Device Handbook, Volume 1

TriMatrix Memory

Figure2–22.M4K RAM Block LAB Row Interface

C4 InterconnectR4 InterconnectDirect link interconnectto adjacent LAB1636dataoutDirect link interconnectto adjacent LABDirect link interconnectfrom adjacent LABM4K RAMBlockdataincontrolsignalsclocksbyteenableDirect link interconnectfrom adjacent LABaddress6M4K RAM Block LocalInterconnect RegionLAB Row ClocksM-RAM Block

The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:

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True dual-port RAMSimple dual-port RAMSingle-port RAMFIFO

You cannot use an initialization file to initialize the contents of an M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed.

Stratix II Device Handbook, Volume 1