Stop = 2’b10, Clear = 2’b11; always @( ③ )//在Clock上升沿 if ( ④ )//Reset为低电平 begin state <= Idle; F<=0; G<=0; end else case( ⑤ ) idle: begin if (A) state <= Start; G<=0; end ⑥ : if (!A) state <= Stop; Stop: begin if (A) state <= Clear; F <= 1; end Clear: begin if (!A) state <=Idle; F<=0; G<=1; end ⑦ ⑧ 3. 根据状态转移图，仔细阅读下列程序，完成填空。（10分） module ztj (CLK, RST, SINPUT,COMOUT ); input CLK, RST; input [1:0] SINPUT; output [3:0]COMOUT; reg [3:0] COMOUT; parameter S0=0, S1=1, S2=2, S3=3, S4=4; reg [ ⑴ :0] C_ST,NEXT_STATE; always@(posedge CLK or negedge RST) begin if (!RST) C_ST<=S0; else C_ST<= ⑵ ; 共 7 页 第 6 页 请注意：答案必须写在答题纸上（写在试卷上无效）。
end always@( C_ST or SINPUT) begin case(C_ST) S0: begin COMOUT<= ⑶ ; if (SINPUT= = ⑷ ) NEXT_STATE<= ⑸ ; else if(SINPUT= = ⑹ ) NEXT_STATE<= ⑺ ; else NEXT_STATE<= ⑻ ; end S1: begin COMOUT<= ⑼ ; if (SINPUT= = ⑽ ) NEXT_STATE<=S1; else NEXT_STATE<=S2; end S2: begin COMOUT<= ⑾ ; if (SINPUT= = ⑿ ) NEXT_STATE<= ⒀ ; else if(SINPUT= = ⒁ ) NEXT_STATE<= ⒂ ; else NEXT_STATE<=S3; end S3: begin COMOUT<= ⒃ ; if (SINPUT= = ⒄ ) NEXT_STATE<=S3; else NEXT_STATE<=S4; end S4: begin COMOUT<= ⒅ ; NEXT_STATE<=S0; end default: NEXT_STATE<=S0; （19） （20） endmodule 共 7 页 第 7 页
通信电子电路及EDA技术B
