Chapter 6:GTX Transmitter (TX)
TX PRBS Generator
Overview
Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link.
The GTX PRBS block can generate several industry-standard PRBS patterns. Table6-13 lists the available PRBS patterns and their typical uses.
Table 6-13:NamePRBS-7PRBS-23
Pseudo-Random Bit SequencesPolynomial1+X6+X7 (inverted)1+X18+X23 (inverted)1+X28+X31 (inverted)
Length of Consecutive Sequence (bits)Zeros
27–1223–1
723
Typical Use
Used to test channels with 8B/10B.
ITU-T Recommendation O.150, Section 5.6. One of the
recommended test patterns in the SONET specification.ITU-T Recommendation O.150, Section 5.8. A recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.
PRBS-31
231
–131
Ports and Attributes
Table6-14 defines the TX PRBS generator ports.
Table 6-14:
TX PRBS Generator Ports
Direction
Clock Domain
Description
Transmitter test pattern generation control. A pseudo-random bit sequence (PRBS) is generated by enabling the test pattern generation circuit.
TXENPRBSTST0[1:0]TXENPRBSTST1[1:0]
00: Test pattern generation off (standard operation mode)
In
TXUSRCLK2
01: Enable 27–1 PRBS generation10: Enable 223–1 PRBS generation11: Enable 231–1 PRBS generation
Because PRBS patterns are deterministic, the receiver can check the received data against a sequence of its own PRBS generator.
Port
There are no attributes in this section.
Description
Each GTX transceiver includes a built-in PRBS generator. This feature can be used in
conjunction with other test features, such as loopback and the built-in PRBS checker, to run tests on a given channel.
To use the PRBS generator, the PRBS test mode is selected using the TXENPRBSTST port. Table6-14 lists the available settings.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Parallel In to Serial Out
Parallel In to Serial Out
Overview
The Parallel In to Serial Out (PISO) block is the heart of the GTX TX datapath. It serializes parallel data from the PCS using a high-speed clock from the shared PMA PLL.
The PISO block serializes 16 or 20 bits per parallel clock cycle, depending on the internal data width for the tile (INTDATAWIDTH). The clock rate is determined by the shared PMA PLL rate, divided by a local TX divider.
Ports and Attributes
Table6-15 defines the TX PISO ports.Table 6-15:
Port
TX PISO Ports
Direction
Clock Domain
Description
Specifies the width of the internal datapath for the entire GTX_DUAL tile. This shared port is also described in “Shared PMA PLL,” page 86.0: Internal datapath is 16 bits wide1: Internal datapath is 20 bits wide
INTDATAWIDTHInAsync
Table6-16 defines the TX PISO attributes.
Table 6-16:
TX PISO Attributes
Type
Description
This shared attribute activates the built-in 5x digital oversampling circuits in both GTX transceivers. Oversampling must be enabled when running the GTX transceivers at line rates between 150Mb/s and 750Mb/s.
OVERSAMPLE_MODE
Boolean
TRUE: Built-in 5x digital oversampling enabled for both GTX transceivers on the tile
FALSE: Digital oversampling disabled
See “Oversampling,” page 185 for more details about 5x digital oversampling.
PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1
Integer
Sets the divider for the TX line rate for the individual GTX transceiver. The divider can be set to 1, 2, or 4.
Attribute
Description
Equation6-5 shows how to calculate the TX line rate when operating without oversampling (OVERSAMPLE_MODE = FALSE).
PLL Clock Rate×2
Tx Line Rate=----------------------------------------------------------PLL_TXDIVSEL_OUT
When oversampling is activated, use Equation6-6 to calculate the line rate.
PLL Clock Rate×
Tx Line Rate=----------------------------------------------------------2-----------PLL_TXDIVSEL_OUT×5
Equation6-5
Equation6-6
See “Oversampling,” page 185 for more information about oversampling.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Figure6-24 illustrates the rise times associated with the receiver present and receiver absent conditions, along with the detection threshold.
X-Ref Target - Figure 6-24τ? RTERMCCH < 180 nsVDDrcvRefReceiver AbsentReceiver PresentVDD – VSWING/2τ? 1/2RTERMCCHrcvDlyτ? 2RTERMCAC > 6000 nsTimeUG198_c6_24_101207Figure 6-24:Receive Detection Thresholds
When the PHY has completed the receiver detect sequence, it asserts PHYSTATUS for one clock and drives the RXSTATUS signals to the appropriate code. After the receiver
detection is completed (as signaled by the assertion of PHYSTATUS), TXDETECTRX must be deasserted. Figure6-25 shows this process.
X-Ref Target - Figure 6-25TXUSRCLK2TXDETECTRXRXPOWERDOWN[1:0]TXPOWERDOWN[1:0]10bPHYSTATUSRXUSRCLK2RXSTATUS[2:0]000bStatusUG198_c6_25_101207Figure 6-25:Receiver Detect Waveforms
RocketIO GTX Transceiver User Guide
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TX Out-of-Band/Beacon Signaling
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-5FGG456C中文规格书 - 图文
