Tables4–98 through 4–105 show the maximum DCD in absolution
derivation for different I/O standards on StratixIIGX devices. Examples are also provided that show how to calculate DCD as a percentage.Table4–98.Maximum DCD for Non-DDIO Output on Row I/O PinsRow I/O Output Standard
3.3-V LVTTTL3.3-V LVCMOS2.5 V1.8 V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class I1.8-V HSTL Class I1.5-V HSTL Class ILVDS
Maximum DCD (ps) for Non-DDIO Output-3 Devices
2451251051801651159555808555
-4 and -5 Devices
2751551351801951451258510011580
Unit
pspspspspspspspspspsps
Here is an example for calculating the DCD as a percentage for a non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 ClassII, the maximum DCD is 95ps (see Table4–99). If the clock frequency is 267MHz, the clock period T is:
T = 1/ f = 1 / 267MHz = 3.745ns = 3,745psTo calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745ps/2 – 95ps) / 3,745ps = 47.5% (for low boundary)
(T/2 + DCD) / T = (3,745ps/2 + 95ps) / 3,745ps = 52.5% (for high boundary)
Table4–100.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Note(1)
Input I/O Standard (No PLL in Clock Path)
Maximum DCD (ps) for Row DDIO Output I/O
Standard
3.3-V LVTTL3.3-V LVCMOS2.5 V1.8 V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class I1.8-V HSTL Class I1.5-V HSTL Class ILVDS
TTL/CMOS3.3 and2.5 V
260210195150255175170155150150180
SSTL-22.5 V
14510085851406560556055180
SSTL/HSTL1.8 and1.5 V
14510085851406560506055180
LVDS3.3 V
11065751201057075909590180
Unit
1.8 and1.5 V
380330315265370295290275270270180
pspspspspspspspspspsps
Therefore, the DCD percentage for the output clock is from 48.4% to 51.6%.
Table4–101.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5 DevicesNote(1)Maximum DCD (ps) for Row DDIO Output I/O
Standard
3.3-V LVTTL3.3-V LVCMOS2.5 V1.8 V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class I1.8-V HSTL Class I1.5-V HSTL Class ILVDS
Input I/O Standard (No PLL in the Clock Path)TTL/CMOS3.3/2.5V
440390375325430355350335330330180
SSTL-22.5V
170120105901608580656060180
SSTL/HSTL1.8/1.5V
160110951001557570657070180
LVDS3.3V
10575901351008590105110105180
Unit
1.8/1.5V
495450430385490410405390385390180
pspspspspspspspspspsps
(1)Table4–101 assumes the input clock has zero DCD.
Table4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of2) Note(1)Maximum DCD (ps) for DDIO Column Output I/O
Standard
3.3-V LVTTL3.3-V LVCMOS2.5 V1.8 V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class I
Input IO Standard (No PLL in the Clock Path)TTL/CMOS3.3/2.5V
260210195150255175170155
SSTL-22.5V
1451008585140656055
SSTL/HSTL1.8/1.5V
1451008585140656050
HSTL121.2V
1451008585140656050
Unit
1.8/1.5V
380330315265370295290275
pspspspspspspsps
Table4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 2 of2) Note(1)Maximum DCD (ps) for DDIO Column Output I/O
Standard
SSTL-18 Class II1.8-V HSTL Class I1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class II1.2-V HSTLLVPECL
Input IO Standard (No PLL in the Clock Path)TTL/CMOS3.3/2.5V
140150150150125240180
SSTL-22.5V
7060605585155180
SSTL/HSTL1.8/1.5V
7060605585155180
HSTL121.2V
7060605585155180
Unit
1.8/1.5V
260270270270240360180
pspspspspspsps
(1)Table4–102 assumes the input clock has zero DCD.
Table4–103.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note(1)Maximum DCD (ps) for DDIO Column Output I/O
Standard
3.3-V LVTTL3.3-V LVCMOS2.5 V1.8 V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class II1.8-V HSTL Class I1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class IILVPECL(1)
Input IO Standard (No PLL in the Clock Path)TTL/CMOS
3.3/2.5V
440390375325430355350335320330330330330180
SSTL-22.5V
170120105901608580657060606090180
SSTL/HSTL1.8/1.5V
1601109510015575706580707070100180
Unit
1.8/1.5V
495450430385490410405390375385385390360180
pspspspspspspspspspspspspsps
Table4–103 assumes the input clock has zero DCD.
FPGA可编程逻辑器件芯片EP3SE260H780C4N中文规格书 - 图文
