BL24C64A

由天下分享时间：2025/1/18 6:42:16 加入收藏我要投稿点赞

BL24C64A 64K bits (8,192×8)

Features

? ?

Compatible with all I2C bidirectional data transfer protocol

Memory array:

– 64 Kbits (8 Kbytes) of EEPROM – Page size: 32 bytes

– Additional Write lockable page

Single supply voltage and high speed: – 1.7V-5.5V – 1 MHz

Random and sequential Read modes Write:

– Byte Write within 3 ms

? ? ?

? ?

Page Write within 3 ms

– Partial Page Writes Allowed

Write Protect Pin for Hardware Data Protection Schmitt Trigger, Filtered Inputs for Noise Suppression High-reliability

– Endurance: 1 Million Write Cycles – Data Retention: 100 Years

Enhanced ESD/Latch-up protection – HBM 8000V

8-lead PDIP/SOP/TSSOP/UDFN and TSOT23-5 packages

–

Description

The BL24C64A provides 65536 bits of serial

electrically erasable and programmable read-only memory (EEPROM), organized as 8192 words of 8 bits each.

The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.

The BL24C64A offers an additional page, named the Identification Page (32 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.

Pin Configuration

８-lead PDIP８-lead SOP８-lead TSSOP８-pad DFN5-lead TSOT23-5WPVCC8VCC7WPA0A1１２87VCCWPA0A1１２87VCCWPA0A1１２87VCCWPSCLA0A112５４A2GND３４65SCLSDAA2GND３４65SCLSDAA2GND３４65A2GND3465SCLSDA１２３SDASCLGNDSDA

BL24C64A 64K bits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

1-19

BL24C64A 64K bits (8,192×8)

Pin Descriptions

Pin NameA0-A2SDASCLWPGNDVcc TypeII/OIIPPTable 1 FunctionsAddress InputsSerial DataSerial Clock InputWrite ProtectGroundPower Supply Block Diagram

VccGND WPSCLSDASTART STOPLOGICENSERIAL CONTROLLOGICLOADCCMPDEVICE ADDRESSCOMPARATORLOADINCDATA RECOVERYHIGH VOLTAGEPUMP/TIMINGX DECODERA0A1A2DATA WORDADRESS COUNTEREEPROMY DECODERSERIAL MUXDINDOUT/ACKNOWLEDGEDOUT

Figure 1

BL24C64A 64K bits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

2-19

BL24C64A 64K bits (8,192×8)

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the BL24C64A. Eight 64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

WRITE PROTECT (WP): The BL24C64A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2.

WP Pin Status At VCC At GND BL24C64A Full(64K) Array Normal Read/Write Operations Table 2

Functional Description

1. Memory Organization

BL24C64A, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit data word address for random word addressing.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.

SDASCLDATA STABLEDATA CHANGEDATA STABLEFigure 2. Data Validity

BL24C64A 64K bits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

3-19

BL24C64A 64K bits (8,192×8)

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).

SDASCLSTARTSTOPFigure 3. Start and Stop Definition

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a \acknowledge that it has received each word. This happens during the ninth clock cycle.

SCL189DATA INDATA OUTSTARTACKNOWLEDGEFigure 4. Output Acknowledge

STANDBY MODE: The BL24C64A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition.

BL24C64A 64K bits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

4-19

BL24C64A 64K bits (8,192×8)

3. Device Addressing

The 64K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5)

MSB1010A2A1A0LSBR/W

Figure 5. Device Address

The device address word consists of a mandatory \shown. This is common to all the Serial EEPROM devices.

The 64K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a \return to a standby state.

DATA SECURITY: The BL24C64A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC.

4. Write Operations

BYTE WRITE: A write operation requires two 8-bit data word address (see Figure 6) following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a \and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a \and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7).

B15B14B13B12B11B10B9B8

B7B6B5B4B3B2B1B0

Figure 6. Data Word Address

STARTSDA LINEMSBLRAS/CBWKLASCBKLASCBKLASCBKWRITESTOPDEVICE ADDRESSFIRST WORD ADDRESSSECOND WORD ADDRESSDATANote.1*=DON'T’T CARE bitsFigure 7. Byte Write

BL24C64A 64K bits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

5-19