PLL
When using the StratixII and StratixIIGX top and bottom I/O banks (I/O banks 3, 4, 7, or8) to interface with a DDR memory, at least one PLL with two outputs is needed to generate the system clock and the write clock. The system clock generates the DQS write signals, commands, and addresses. The write clock is either shifted by –90° or 90° from the system clock and is used to generate the DQ signals during writes. For DDR and DDR2 SDRAM interfaces above 200MHz, Altera also recommends a second read PLL to help ease resynchronization.
When using the StratixII and StratixIIGX side I/O banks 1, 2, 5, or 6 to interface with DDR SDRAM devices, two PLLs may be needed per I/O bank for best performance. Since the side I/O banks do not have
dedicated circuitry, one PLL captures data from the DDR SDRAM and another PLL generates the write signals, commands, and addresses to the DDR SDRAM device. StratixII and StratixIIGX side I/O banks can support DDR SDRAM up to 150 MHz.
Enhancements In StratixII and Stratix II GX Devices
StratixII and StratixIIGX external memory interfaces support differs from Stratix external memory interfaces support in the following ways:
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A PLL output can now be used as the input reference clock to theDLL.
The shifted DQS signal can now go into the logic array.
The DLL in StratixII and StratixIIGX devices has more phase-shiftoptions than in Stratix devices. It also has the option to add phaseoffset settings.
StratixII and StratixIIGX devices have DQS logic blocks with eachDQS pin that helps with fine tuning the phase shift.
The DQS delay settings can be routed from the DLL into the logicarray. You can also bypass the DLL and send the DQS delay settingsfrom the logic array to the DQS logic block.
StratixII and StratixIIGX devices support DQSn pins.
The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.The DQS pins have been enhanced with the DQS postamble circuitry.
Conclusion
StratixII and StratixIIGX devices support SDR SDRAM, DDR SDRAM, DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories. StratixII and StratixIIGX devices feature high-speed interfaces that transfer data between external memory devices at up to 300 MHz/600 Mbps. DQS phase-shift circuitry and DQS logic blocks within the
StratixII and StratixIIGX devices allow you to fine-tune the phase shifts for the input clocks or strobes to properly align clock edges as needed to capture data.
Stratix II Device Handbook, Volume 2
External Memory Interfaces in StratixII and StratixIIGX Devices
Referenced Documents
This chapter references the following documents:
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AN 325: Interfacing RLDRAM II with StratixII & StratixGX DevicesAN326: Interfacing QDRII & QDRII+ SRAM with StratixII, Stratix, &StratixGX Devices
AN 327: Interfacing DDR SDRAM with StratixII DevicesAN 328: Interfacing DDR2 SDRAM with StratixII DevicesDC & Switching Characteristics of Stratix III Devices chapter involume2 of the Stratix III Device Handbook
Document
Revision History
Table3–11 shows the revision history for this chapter.
Table3–11.Document Revision History Date and Document Version
January 2008, v4.5No change
Minor text edits.
For the Stratix II GX Device Handbook only:
Formerly chapter 8. The chapter number changed due to the addition of the StratixIIGX Dynamic Reconfiguration chapter. No content change.Updated the “Phase Offset Control” section.Updated Figure3–2.Updated Table3–1.
Added Table3–4 and Table3–6.Updated Note(1) to Figure3–10.
February 2007 v4.3
April 2006, v4.2No change
Added the “Document Revision History” section to this chapter.
Chapter updated as part of the Stratix II Device Handbook update.
Formerly chapter 7. Chapter number change only due to chapter addition to Section I in February2006; no content change.
—
Changes Made
Added the “Referenced Documents” section.
Summary of Changes
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May 2007,v4.4
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December 2005 Chapter updated as part of the Stratix II Device v4.1Handbook update.October 2005v4.0
Added chapter to the Stratix II GX Device Handbook.
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Stratix II Device Handbook, Volume 2
StratixII and StratixIIGX I/O Standards Support
Stratix II Device Handbook, Volume 2
Selectable I/O Standards in StratixII and StratixIIGX Devices
Figure4–5.1.8-V HSTL Class I Termination
VTT = 0.9 VOutput Buffer50 ΩZ = 50 ΩVREF = 0.9 VInput BufferFigure4–6.1.8-V HSTL Class II Termination
VTT = 0.9 VVTT = 0.9 V50 ΩZ = 50 ΩVREF = 0.9 VOutput Buffer50 ΩInput Buffer1.5-V HSTL Class I and 1.5-V HSTL Class II
The 1.5-V HSTL standard is formulated under EIA/JEDEC Standard, EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits.
The 1.5-V HSTL I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard defines single-ended input and output specifications for all
HSTL-compliant digital integrated circuits. The 1.5-V HSTL I/O standard in StratixII and StratixIIGX devices are compatible with the 1.8-V HSTL I/O standard in APEX?20KE, APEX20KC, and in StratixII and
StratixIIGX devices themselves because the input and output voltage thresholds are compatible (Figures4–7 and 4–8). 1
StratixII and StratixIIGX devices support both input and output levels with VREF and VTT.
Stratix II Device Handbook, Volume 2
Selectable I/O Standards in StratixII and StratixIIGX Devices
Figures4–12 and 4–13 shows details on differential SSTL-18 termination. StratixII and StratixIIGX devices support differential SSTL-18 I/O standards in pseudo-differential mode, which is implemented by using two SSTL-18 single-ended buffers.
The QuartusII software only supports pseudo-differential standards on the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is used. Two single-ended output buffers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. A proper VREF voltage is required for the two single-ended input buffers to implement a pseudo-differential input. In this case, only the positive polarity input is used in the speed path while the negative input is not connected internally. In other words, only the non-inverted pin is required to be specified in your design, while the QuartusII software automatically generates the inverted pin for you.
Although the QuartusII software does not support pseudo-differential SSTL-18 I/O standards on the left and right I/O banks, you can
implement these standards at these banks. You need to create two pins in the designs and configure the pins with single-ended SSTL-18 standards. However, this is limited only to pins that support the differential pin-pair I/O function and is dependent on the single-ended SSTL-18 standards support at these banks.
Figure4–12.Differential SSTL-18 Class I Termination
VTT = 0.9 VVTT = 0.9 VDifferentialTransmitter25 Ω50 Ω50 ΩDifferentialReceiver Z0 = 50 Ω25 ΩZ0 = 50 ΩStratix II Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S10F484I6N中文规格书 - 图文
