5.DC & Switching
Characteristics
SII51005-4.4
Operating Conditions
Stratix?II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades.
Tables5–1 through 5–32 provide information about absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for StratixII devices.
Absolute Maximum Ratings
Table5–1 contains the absolute maximum ratings for the StratixII device family.
Table5–1.StratixII Device Absolute Maximum RatingsSymbol
VCCINTVCCIOVCCPDVCCAVCCDVIIOUTTSTGTJ(1)(2)(3)(4)
Notes(1), (2), (3)
Minimum
–0.5–0.5–0.5–0.5–0.5–0.5–25
Parameter
Supply voltageSupply voltageSupply voltage
Analog power supply for PLLs
Conditions
With respect to groundWith respect to groundWith respect to groundWith respect to ground
Maximum
1.84.64.61.81.84.640150125
Unit
VVVVVVmA°C°C
Digital power supply for PLLsWith respect to groundDC input voltage (4)DC output current, per pinStorage temperatureJunction temperature
No bias
BGA packages under bias
–65–55
Notes to Tables5–1
See the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table5–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table5–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100mA and periods shorter than 20ns.
Document Revision History
Stratix II Device Handbook, Volume 1
PLLs in StratixII and StratixIIGX Devices
Table1–6.I/O Standards Supported for Enhanced PLL Pins(Part 2 of2) Note(1)
I/O Standard
Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I Differential SSTL-18 Class II 1.8-V differential HSTL Class I 1.8-V differential HSTL Class II 1.5-V differential HSTL Class I 1.5-V differential HSTL Class II LVDS
HyperTransport technologyDifferential LVPECL Note to Table1–6:(1)
The enhanced PLL external clock output bank does not allow a mixture of both single-ended and differential I/O standards.
Input
INCLKvvvvvvvvvv
FBINvvvvvvvvvv
OutputEXTCLKvvvvvvvvvv
Table1–7 shows the physical pins and their purpose for the StratixII and Stratix II GX enhanced PLLs. For inclk port connections to pins see “Clock Control Block” on page1–86.
Table1–7.StratixII and Stratix II GX Enhanced PLL Pins (Part 1 of3)
Pin
CLK4p/nCLK5p/nCLK6p/nCLK7p/nCLK12p/nCLK13p/nCLK14p/nCLK15p/nPLL5_FBp/n
Note(1)
Description
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.Single-ended or differential pins that can drive the fbin port for PLL 5.
Stratix II Device Handbook, Volume 2
Enhanced PLLs
Table1–7.StratixII and Stratix II GX Enhanced PLL Pins (Part 2 of3)
Pin
PLL6_FBp/nPLL11_FBp/nPLL12_FBp/nPLL_ENA
PLL5_OUT[2..0]p/nPLL6_OUT[2..0]p/nPLL11_OUT[2..0]p/nPLL12_OUT[2..0]p/nVCCA_PLL5GNDA_PLL5VCCA_PLL6GNDA_PLL6VCCA_PLL11GNDA_PLL11VCCA_PLL12GNDA_PLL12VCCD_PLLVCC_PLL5_OUT
Note(1)
Description
Single-ended or differential pins that can drive the fbin port for PLL 6.Single-ended or differential pins that can drive the fbin port for PLL 11.Single-ended or differential pins that can drive the fbin port for PLL 12.Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use this pin, connect it to ground.
Single-ended or differential pins driven by C[5..0] ports from PLL 5.Single-ended or differential pins driven by C[5..0] ports from PLL 6.Single-ended or differential pins driven by C[5..0] ports from PLL 11.Single-ended or differential pins driven by C[5..0] ports from PLL 12.
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not used.
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not used.
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not used.
Analog ground for PLL 11. You can connect this pin to the GND plane on the board.
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not used.
Analog ground for PLL 12. You can connect this pin to the GND plane on the board.
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not used.
External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from PLL 5.
External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from PLL 6.
External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs from PLL 11.
VCC_PLL6_OUT
VCC_PLL11_OUT
Stratix II Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP2S40B724C7N中文规格书 - 图文
