Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58:Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Input Frequency RangesFCLKIN
CLKIN_FREQ_DLL_LFCLKIN_FREQ_DLL_HF
Input Pulse RequirementsCLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
FCLKIN ≤ 100 MHzFCLKIN > 100 MHz
LowHighAllAll
40E%––––
Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input
–
60U%
40E%–––––
60U%
--pspsnsns
Frequency for the CLKIN input
LowHigh
18(2)48
167(3)280(3)
18(2)48
167(3)280(3)(4)
MHzMHz
Description
Frequency Mode/FCLKIN Range
Min
-5Max
Min
-4Max
Units
Input Clock Jitter Tolerance and Delay Path Variation(5)CLKIN_CYC_JITT_DLL_LFCLKIN_CYC_JITT_DLL_HFCLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_DLL_HF CLKFB_DELAY_VAR_EXT
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
±300±150±1±1
±300±150±1±1
Notes:
1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.3.4.5.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table60.
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table64.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 69:Types of Pins on Spartan-3 FPGAs (Cont’d)
Pin Type/ Color CodeVREF
DescriptionPin Name
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in IO/VREF_#
the same bank, provides a reference voltage input for certain I/O standards. If used IO_Lxxy_#/VREF_#for a reference voltage within a bank, all VREF pins within the bank must be connected.
Dedicated ground pin. The number of GND pins depends on the package used. All GNDmust be connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the VCCAUXpackage used. All must be connected to +2.5V.
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the package used. All must be connected to +1.2V.
VCCINT
GNDVCCAUXVCCINTVCCO
Dedicated I/O bank, output buffer power supply pin. Along with other VCCO pins in VCCO_#
the same bank, this pin supplies power to the output buffers within the I/O bank and CP132 and TQ144 Packages Only:sets the input threshold voltage for some I/O standards.VCCO_LEFT, VCCO_TOP,
VCCO_RIGHT, VCCO_BOTTOMDual-purpose pin that is either a user-I/O pin or an input to a specific global buffer IO_Lxxy_#/GCLK0, input. Every package has eight dedicated GCLK pins.IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2, IO_Lxxy_#/GCLK3, IO_Lxxy_#/GCLK4, IO_Lxxy_#/GCLK5, IO_Lxxy_#/GCLK6, IO_Lxxy_#/GCLK7This package pin is not connected in this specific device/package combination but N.C.may be connected in larger devices in the same package.
GCLK
N.C.Notes:
1.
# = I/O bank number, an integer between 0 and 7.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indicates differential output capability. The “xx” field is a two-digit integer, unique to each bank that identifies a differential pin-pair. The ‘y’ field is either ‘P’ for the true signal or ‘N’ for the inverted signal in the differential pair. The ‘#’ field is the I/O bank number.
Pin Definitions
Table70 provides a brief description of each pin listed in the Spartan-3 FPGA pinout tables and package footprint diagrams. Pins are categorized by their pin type, as listed in Table69. See Detailed, Functional Pin Descriptions for more information.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2V80-4FF1152C中文规格书
