DDR3L SDRAM
MT41K1G4 – 128 Meg x 4 x 8 banksMT41K512M8 – 64 Meg x 8 x 8 banksMT41K256M16 – 32 Meg x 16 x 8 banksDescription
DDR3L SDRAM (1.35V) is a low voltage version of theDDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM(Die Rev :E) data sheet specifications when running in1.5V compatible mode.
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Self refresh temperature (SRT)Automatic self refresh (ASR)Write leveling
Multipurpose registerOutput driver calibration
Features
?VDD = VDDQ = 1.35V (1.283–1.45V)
?Backward compatible to VDD = VDDQ = 1.5V ±0.075V–Supports DDR3L devices to be backward com-patible in 1.5V applications
?Differential bidirectional data strobe?8n-bit prefetch architecture
?Differential clock inputs (CK, CK#)?8 internal banks
?Nominal and dynamic on-die termination (ODT)for data, strobe, and mask signals
?Programmable CAS (READ) latency (CL)
?Programmable posted CAS additive latency (AL)?Programmable CAS (WRITE) latency (CWL)
?Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])
?Selectable BC4 or BL8 on-the-fly (OTF)?Self refresh mode?TC of 105°C
–64ms, 8192-cycle refresh up to 85°C
–32ms, 8192-cycle refresh at >85°C to 95°C–16ms, 8192-cycle refresh at >95°C to 105°C
Options
?Configuration–1 Gig x 4–512 Meg x 8–256 Meg x 16
?FBGA package (Pb-free) – x4, x8–78-ball (9mm x 10.5mm) Rev. E–78-ball (7.5mm x 10.6mm) Rev. N–78-ball (8mm x 10.5mm) Rev. P?FBGA package (Pb-free) – x16–96-ball (9mm x 14mm) Rev. E–96-ball (7.5mm x 13.5mm) Rev. N–96-ball (8mm x 14mm) Rev. P?Timing – cycle time
–938ps @ CL = 14 (DDR3-2133)–1.07ns @ CL = 13 (DDR3-1866)–1.25ns @ CL = 11 (DDR3-1600)?Operating temperature
–Commercial (0°C ?? TC ?? +95°C)–Industrial (–40°C ?? TC ?? +95°C)–Automotive (–40°C ?? TC ?? +105°C)?Revision
Marking
1G4512M8256M16RHRGDAHALYTW-093-107-125NoneITAT:E/:N/:P
Table 1: Key Timing Parameters
Speed Grade-093 1, 2-107 1-125Notes:
Data Rate (MT/s)213318661600Target tRCD-tRP-CL14-14-1413-13-1311-11-11tRCD (ns)tRP (ns)CL (ns)13.0913.9113.7513.0913.9113.7513.0913.9113.751.Backward compatible to 1600, CL = 11 (-125).2.Backward compatible to 1866, CL = 13 (-107).
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4Gb_DDR3L.pdf - Rev. R 09/18 EN
4Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
ODT Characteristics
The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to theDQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target valuesand a functional representation are listed in Table 32 and Table 33 (page 61). The indi-vidual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:?RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off?RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off
Figure 23: ODT Levels and I-V Characteristics
Chip in termination mode
ODTVDDQ
IPUToothercircuitrysuch as RCV, . . .RTT(PU)IOUTRTT(PD)IPDVSSQDQVOUT
IOUT = IPD - IPU
Table 32: On-Die Termination DC Electrical Characteristics
Parameter/ConditionRTT effective impedanceDeviation of VM with respect toVDDQ/2Notes:
SymbolRTT(EFF)?VM–5MinNomMax5Unit%Notes1, 21, 2, 3See Table 33 (page 61)1.Tolerance limits are applicable after proper ZQ calibration has been performed at a
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity (page62)if either the temperature or voltage changes after calibration.
2.Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current
I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
VIH(AC) - VIL(AC)
RTT =
I(VIH(AC)) - I(VIL(AC))3.Measure voltage (VM) at the tested pin with no load:
?VM =
2 × VM
– 1× 100
VDDQ
4.For IT and AT devices, the minimum values are derated by 6% when the device operates
between –40°C and 0°C (TC).
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Electrical Characteristics and AC Operating Conditions
Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire tableDDR3L-1866ParameterClock period average:DLL disable modeTC = 0°C to 85°CTC = >85°C to 95°CSymboltCK09005aef85af8fa84Gb_DDR3L.pdf - Rev. R 09/18 ENDDR3L-2133Max780039000.530.536050Min880.470.47–50–40MIN = tCK (AVG) MIN +tJITper MIN; MAX =tCK (AVG) MAX +tJITper MAX psMax780039000.530.535040UnitnsnsCKCKpspsNotes9, 424210, 111212MinClock Timing880.470.47–60–50(DLL_DIS)tCK (AVG)tCH (AVG)tCL (AVG)tJITpertJITper,lcktCK (ABS)Clock period average: DLL enable modeHigh pulse width averageLow pulse width averageClock period jitterClock absolute periodDLL lockedDLL lockingSee Speed Bin Tables for tCK range allowed ns4Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating Conditions1313Clock absolute high pulse widthClock absolute low pulse widthCycle-to-cycle jitterDLL lockedDLL lockingtCH (ABS)tCL (ABS)tJITcctJITcc,lck0.430.43120100––0.430.43120100––tCK14151616(AVG)tCK(AVG)psps09005aef85af8fa84Gb_DDR3L.pdf - Rev. R 09/18 ENTable 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire tableDDR3L-1866ParameterCumulative error across2 cycles3 cycles4 cycles5 cycles6 cycles7 cycles8 cycles9 cycles10 cycles11 cycles12 cyclesn = 13, 14 . . . 49, 50cyclesData setup time toDQS, DQS#Data hold time fromDQS, DQS#Base (specification)@ 2 V/nsVREF @ 2 V/nsBase (specification)@ 2 V/nsVREF @ 2 V/nsMinimum data pulse widthDQS, DQS# to DQ skew, per accessDQ output hold time from DQS, DQS#DQ Low-Z time from CK, CK#DQ High-Z time from CK, CK#DQS, DQS# rising to CK, CK# risingDQS, DQS# differential input low pulse widthtDIPWtDHDDR3L-2133Max88105117126133139145150154158161Min–74–87–97–105–111–116–121–125–128–132–134Max748797105111116121125128132134UnitpspspspspspspspspspspspsNotes171717171717171717171717SymboltERR2pertERR3pertERR4pertERR5pertERR6pertERR7pertERR8pertERR9pertERR10pertERR11pertERR12pertERRnperMin–88–105–117–126–133–139–145–150–154–158–1614Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating ConditionstERRnper MIN = (1 + 0.68ln[n]) × tJITper MINtERRnper MAX = (1 + 0.68ln[n]) × tJITper MAXDQ Input TimingtDS7013575110320DQ Output Timing–0.38–390––0.270.45–––––85–1951950.270.5555120.560105280–0.38–360––0.270.45–––––75–1801800.270.55pspspspspspstCK18, 1919, 2018, 1919, 2041(AC130)(DC90)tDQSQtQHtLZDQtHZDQ2122, 2322, 2325(AVG)pspsCKCKDQ Strobe Input TimingtDQSStDQSL4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normalmode can be used. Figure 49 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stopdriving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memo-ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls becomeundefined when DQS no longer remains LOW, and they remain undefined until tMODafter the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after theDQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at~Tb0) until the DRAM is ready for either another rank to be leveled or until the normalmode can be used. After DQS termination is switched off, write level mode should bedisabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid com-mand may be registered by the DRAM. Some MRS commands may be issued after tMRD(at Td1).
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4Gb: x4, x8, x16 DDR3L SDRAMVoltage Initialization/Change
VDD Voltage Switching
After the DDR3L DRAM is powered up and initialized, the power supply can be alteredbetween the DDR3L and DDR3 levels, provided the sequence in Figure 51 is main-tained.
Figure 51: VDD Voltage Switching
TaTb(())(())(())(())Tc(())(())tCKSRXTd(())(())Te(())(())Tf(())(())Tg(())(())Th
(())(())Ti
(())(())Tj
(())(())Tk
CK, CK#
TMIN = 10nsVDD, VDDQ (DDR3)VDD, VDDQ (DDR3L)(())(())(())(())(())(())(())(())(())(())(())(())(())(())(())(())(())(())TMIN = 10nsTMIN = 200μs T = 500μsRESET#
(())(())(())(())(())(())(())(())(())(())(())tISTMIN = 10ns(())(())(())(())(())(())(())(())(())(())(())tDLLKCKE
(())(())(())(())ValidtXPRtIStMRDtMRDtMRDtMODtZQinitCommand
(())(())(())(())Note 1 (())(())(())(())MRS(())(())MRS(())(())MRS(())(())MRS(())(())ZQCL(())(())Note 1 (())(())ValidBA
(())(())(())(())MR2(())(())MR3(())(())MR1(())(())MR0(())(())(())(())(())(())ValidtIStISODT
(())(())(())(())(())(())(((((((())))))))Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW (((((((())))))))(())(())(())(())ValidRTT(())(())(())(())(())(())(())(())(())(())Time break(())Don’t Care
Note:
1.From time point Td until Tk, NOP or DES commands must be applied between MRS and
ZQCL commands.
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MEMORY存储芯片PC28F00AP30TFA中文规格书 - 图文
