Remote System Upgrade
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StratixIII devices contain the remote update feature. For more information about this feature, refer to the Remote System Upgrades with StratixIII Devices in volume 1 of the StratixIII Device Handbook.
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply voltage levels have stabilized on power-up. On power-up, the device does not release nSTATUS until VCCPT, VCCL, VCC, VCCPD, and VCCPGM are above the device’s POR trip point. On power down, brown-out occurs if VCC or VCCL ramps down below the POR trip point and VCC, VCCPD, or VCCPGM drops below the threshold voltage.
In StratixIII devices, a pin-selectable option (PORSEL) is provided that allows you to select a typical POR time setting of 12ms or 100ms. In both cases, you can extend the POR time by using an external component to assert the nSTATUS pin low.
VCCPGM Pins
StratixIII devices offer a new power supply, VCCPGM, for all the dedicated configuration pins and dual function pins. The configuration voltages supported are 1.8 V, 2.5 V, 3.0V, and 3.3V. StratixIII devices do not support the 1.5V configuration.
Use this pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bi-directional pins, and some of the dual functional pins that you use for configuration. With VCCPGM, configuration input buffers do not have to share power lines with the regular I/O buffer in StratixIII devices. The operating voltage for the configuration input pin is independent of the I/O bank’s power supply VCCIO during the configuration. Therefore, no configuration voltage constraints on VCCIO are needed in StratixIII devices.
VCCPD Pins
StratixIII devices have a dedicated programming power supply, VCCPD, which must be connected to 3.3V/3.0V/2.5V to power the I/O pre-drivers, the JTAG input and output pins (TCK, TMS, TDI, TDO, and TRST), and the design security circuitry. 1
VCCPGM and VCCPD must ramp up from 0V to the desired voltage level within 100ms. If these supplies are not ramped up within this specified time, your StratixIII device will not configure successfully. If your system does not allow ramp-up time of 100ms or less, you must hold nCONFIG low until all power supplies are stable.
For more information about the configuration pins power supply, refer to “Device Configuration Pins” on page11–43.
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Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII DevicesFast Passive Parallel Configuration
Figure11–3 shows the configuration interface connections between the StratixIII device and a MAXII device for single device configuration.
Figure11–3.Single Device FPP Configuration Using an External Host
MemoryADDRDATA[7..0]VCCPGM (1)VCCPGM (1)10 kΩ10 kΩStratix III DeviceMSEL[2..0]CONF_DONEnSTATUSnCEnCEOGNDN.C.External Host(MAX II Device orMicroprocessor)GNDDATA[7..0]nCONFIGDCLKNote to Figure11–3:
(1)Connect the resistor to a supply that provides an acceptable input signal for the StratixIII device. VCCPGM should be
high enough to meet the VIH specification of the I/O on the external host. It is recommended to power up allconfiguration system’s I/O with VCCPGM.
Upon power-up, the StratixIII device goes through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately 100ms. When PORSEL is driven high, the POR time is approximately 12ms. During POR, the device resets, holds nSTATUS low, and tri-states all user I/O pins. After the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and configuration, the user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on (after POR) before and during configuration. If nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization. While nCONFIG or nSTATUS is low, the device is in the reset stage. To initiate configuration, the MAXII device must drive the nCONFIG pin from low to high.1
VCC, VCCIO, VCCPGM, and VCCPD of the banks where the configuration and JTAG pins reside must be fully powered to the appropriate voltage levels to begin the configuration process.
When nCONFIG goes high, the device comes out of reset and releases the open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAXII device places the configuration data one byte at a time on the DATA[7..0] pins.1
StratixIII devices receive configuration data on the DATA[7..0] pins and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If you are using the StratixIII decompression feature, design security feature, or both, the configuration data is latched on the rising edge of every fourth DCLK cycle. After the configuration data is latched in, it is processed during the following three DCLK cycles.
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Fast Passive Parallel Configuration
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Fast Passive Parallel Configuration
FPP Configuration Timing
Figure11–6 shows the timing waveform for FPP configuration using a MAXII device as an external host. This waveform shows the timing when the decompression and the design security feature are not enabled.
Figure11–6.FPP Configuration Timing Waveform (Note1), (2)
tCF2ST1tCFGnCONFIG
tCF2CKnSTATUS (3)
tSTATUStCF2ST0ttCF2CDtST2CK(7)CLKCONF_DONE (4)
tCHtCL(5)tDH(6)Byte n-2Byte n-1Byte nDCLKDATA[7..0]
Byte 0Byte 1Byte 2Byte 3User ModetDSUUser I/O
High-ZUser ModeINIT_DONE
tCD2UMNotes to Figure11–6:
(1)You should use this timing waveform when the decompression and design security features are not used.
(2)The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3)Upon power-up, the StratixIII device holds nSTATUS low for the time of the POR delay.(4)Upon power-up, before and during configuration, CONF_DONE is low.
(5)You should not leave DCLK floating after configuration. You should drive it high or low, whichever is more convenient.
(6)DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings.(7)Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Table11–5 defines the timing parameters for StratixIII devices for FPP configuration when the decompression and the design security features are not enabled.
Table11–5.FPP Timing Parameters for StratixIII Devices (Note1)(Part 1 of 2)SymboltCF2CDtCF2ST0tCFGtSTATUStCF2ST1tCF2CKtST2CKtDSUtDHtCHtCLParameternCONFIG low to CONF_DONE low nCONFIG low to nSTATUS lownCONFIG low pulse width nSTATUS low pulse widthnCONFIG high to nSTATUS highnCONFIG high to first rising edge on DCLKnSTATUS high to first rising edge of DCLKData setup time before rising edge on DCLKData hold time after rising edge on DCLKDCLK high timeDCLK low time Minimum——210—10025044Maximum800800—100 (2)100 (2)——————Unitsnsns μs μs μs μsμsnsnsnsnsStratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII DevicesFast Passive Parallel Configuration
Table11–5.FPP Timing Parameters for StratixIII Devices (Note1)(Part 2 of 2)SymboltCLKfMAXtRttCD2UMtCD2CUDCLK periodDCLK frequency Input rise timeInput fall timeCONF_DONE high to user mode (3)CONF_DONE high to CLKUSR enabledParameterMinimum10———204 × maximumDCLK periodtCD2CU + (4,436tCD2UMCCONF_DONE high to user mode with CLKUSR option on× CLKUSRperiod)Notes to Table11–5:
(1)Use these timing parameters when the decompression and design security features are not used.
(2)This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3)The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device.
Maximum—1004040100—UnitsnsMHznsnsμs———Figure11–7 shows the timing waveform for FPP configuration when using a MAXII device as an external host. This waveform shows the timing when the decompression feature, design security feature, or both are enabled.
Figure11–7.FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled (Note1), (2)
tCF2ST1tCFGnCONFIG(3)nSTATUS(4)CONF_DONE
tCF2CDtCF2CKtSTATUStCF2ST0tST2CKtCLtCH(8)DCLKDATA[7..0]
123412tCLK34(7)(7)1Byte 234(5)(6)User ModeUser ModeByte 0tDSUtDHByte 1tDHByte (n-1)Byte nUser I/OHigh-ZINIT_DONE
tCD2UMNotes to Figure11–7:
(1)Use this timing waveform when the decompression feature, design security feature, or both are used.
(2)The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3)Upon power-up, the StratixIII device holds nSTATUS low for the time of the POR delay.(4)Upon power-up, before and during configuration, CONF_DONE is low.
(5)Do not leave DCLK floating after configuration. Drive it high or low, whichever is more convenient.
(6)DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings.
(7)If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to sending
the first DCLK rising edge.
(8)Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S20F484C7中文规格书 - 图文
