Electrical characteristics
2
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.12.2.2ECSPI slave mode timing
Figure36 depicts the timing of ECSPI in slave mode. Table 48 lists the ECSPI slave mode timing characteristics.
ECSPIx_SS_B
CS1
CS2CS6
CS4CS5ECSPIx_SCLK
CS2CS9
ECSPIx_MISO
CS7
ECSPIx_MOSI
CS8
Figure36. ECSPI Slave Mode Timing DiagramTable48. ECSPI Slave Mode Timing Parameters
ID
Parameter
SymboltclktSWtCSLHtSCStHCStSmositHmositPDmiso
Min1543721.5
Half ECSPIx_SCLK period
55444
Max———————19
Unitnsnsnsnsnsnsnsns
CS1ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–WriteCS2ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–WriteCS4ECSPIx_SS_B pulse width
CS5ECSPIx_SS_B Lead Time (CS setup time)CS6ECSPIx_SS_B Lag Time (CS hold time)CS7ECSPIx_MOSI Setup TimeCS8ECSPIx_MOSI Hold Time
CS9ECSPIx_MISO Propagation Delay (CLOAD=20pF)
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Electrical characteristics
4.12.3Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.12.3.1SD/eMMC4.3 (single data rate) AC timing
SD4SD2SD5
SD1
Figure37 depicts the timing of SD/eMMC4.3, and Table 49 lists the SD/eMMC4.3 timing characteristics.
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure37. SD/eMMC4.3 Timing
Table49. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Card Input Clock
SD1
Clock Frequency (Low Speed)
Clock Frequency (SD/SDIO Full Speed/High Speed)Clock Frequency (MMC Full Speed/High Speed)Clock Frequency (Identification Mode)
SD2SD3SD4SD5
Clock Low TimeClock High TimeClock Rise TimeClock Fall Time
fPP1fPP2fPP3fODtWLtWHtTLHtTHL
00010077——
40025/5020/52400——33
kHzMHzMHzkHznsnsnsns
Symbols MinMax
Unit
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6
uSDHC Output Delay
tOD
-6.6
3.6
ns
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MEMORY存储芯片KMPC866TVR133A中文规格书 - 图文
