AD7708/AD7718
PIN FUNCTION DESCRIPTIONSPin No1MnemonicAIN7FunctionAnalog Input Channel 7. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN8. (See ADC Control Register section.)Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN7. (See ADC Control Register section.)Analog Supply VoltageAnalog GroundNegative Reference Input. This reference input can lie anywhere between AGND and AVDD – 1 V.Positive reference input. REFIN(+) can lie anywhere between AVDD and AGND. The nominalreference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a referencerange from 1 V to AVDD.Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN2. (See ADC Control Register Section.)Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN1. (See ADC Control Register section.)Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN4. (See ADC Control Register section.)Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN3. (See ADC Control Register section.)Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN6. (See ADC Control Register section ADCCON.)All analog inputs are referenced to this input when configured in pseudo-differential input mode.Positive reference input/analog input. This input can be configured as a reference input with thesame characteristics as REFIN1(+) or as an additional analog input. When configured as ananalog input this pin provides a programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN10. (See ADC Control Register section.)Negative reference input/analog input. This pin can be configured as a reference or analog input.When configured as a reference input it provides the negative reference input for REFIN2.When configured as an analog input it provides a programmable-gain analog input that can beused as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN9. (See ADC Control Register section.)Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN5. (See ADC Control Register section.)P2 can act as a general-purpose Input/Output bit referenced between AVDD and AGND. Thereis a weak pull-up to AVDD internally on this pin.It is recommended that this pin be tied directly to AGND.P1 can act as a general-purpose Input/Output bit referenced between AVDD and AGND. Thereis a weak pull-up to AVDD internally on this pin.Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-upinternally to DVDD.Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-triggerinput making an opto-isolated interface more robust. The serial clock can be continuous with alldata transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clockwith the information being transmitted to or from the AD7708/AD7718 in smaller batches of data.2AIN83456AVDDAGNDREFIN1(–)REFIN1(+)7AIN18AIN29AIN310AIN411AIN51213AINCOMREFIN2(+)/AIN914REFIN2(–)/AIN1015AIN61617181920P2AGNDP1RESETSCLK–12–REV. 0
AD7708/AD7718
ADC CIRCUIT INFORMATIONThe AD7708/AD7718 incorporates a 10-channel multiplexerwith a sigma-delta ADC, on-chip programmable gain amplifierand digital filtering intended for the measurement of widedynamic range, low frequency signals such as those in weigh-scale,strain-gauge, pressure transducer, or temperature measurementapplications. The AD7708 offers 16-bit resolution while theAD7718 offers 24-bit resolution. The AD7718 is a pin-for-pincompatible version of the AD7708. The AD7718 offers a directupgradable path from a 16-bit to a 24-bit system without requiringany hardware changes and only minimal software changes.These parts can be configured as four/five fully-differentialinput channels or as eight/ten pseudo-differential input chan-nels referenced to AINCOM. The channel is buffered and canbe programmed for one of eight input ranges from ±20 mV to±2.56V. Buffering the input channel means that the part canhandle significant source impedances on the analog input andthat R, C filtering (for noise rejection or RFI reduction) can beplaced on the analog inputs if required. These input channelsare intended to convert signals directly from sensors without theneed for external signal conditioning.The ADC employs a sigma-delta conversion technique to realizeup to 24 bits of no missing codes performance. The sigma-deltamodulator converts the sampled input signal into a digital pulsetrain whose duty cycle contains the digital information. A Sinc3programmable low-pass filter is then employed to decimate themodulator output data stream to give a valid data conversion resultat programmable output rates. The signal chain has two modesof operation, CHOP enabled and CHOP disabled. The CHOP bitin the mode register enables and disables the chopping scheme.Signal Chain Overview (CHOP Enabled, CHOP = 0)filter whose primary function is to remove the quantization noiseintroduced at the modulator. The cutoff frequency and deci-mated output data rate of the filter are programmable via the SFword loaded to the filter register. The complete signal chain ischopped resulting in excellent dc offset and offset drift specifica-tions and is extremely beneficial in applications where drift, noiserejection, and optimum EMI rejection are important factors.With chopping, the ADC repeatedly reverses its inputs. Thedecimated digital output words from the Sinc3 filters, therefore,have a positive offset and negative offset term included. As aresult, a final summing stage is included so that each outputword from the filter is summed and averaged with the previousfilter output to produce a new valid output result to be writtento the ADC data register. The programming of the Sinc3 deci-mation factor is restricted to an 8-bit register SF, the actualdecimation factor is the register value times 8. The decimatedoutput rate from the Sinc3 filter (and the ADC conversion rate)will therefore befADC=wherefADC in the ADC conversion rate.SF is the decimal equivalent of the word loaded to the filterregister.fMOD is the modulator sampling rate of 32.768 kHz.The chop rate of the channel is half the output data rate:11××fMOD38×SFfCHOP=12×fADCWith CHOP = 0, chopping is enabled, this is the default and givesoptimum performance in terms of drift performance. With choppingenabled, the available output rates vary from 5.35Hz (186.77 ms)to 105.03 Hz (9.52 ms).A block diagram of the ADC inputchannel with chop enabled is shown in Figure 4.The sampling frequency of the modulator loop is many timeshigher than the bandwidth of the input signal. The integrator inthe modulator shapes the quantization noise (which results fromthe analog-to-digital conversion) so that the noise is pushedtoward one-half of the modulator frequency. The output of thesigma-delta modulator feeds directly into the digital filter. Thedigital filter then band-limits the response to a frequency signifi-cantly lower than one-half of the modulator frequency. In thismanner, the 1-bit output of the comparator is translated into aband limited, low noise output from the AD7708/AD7718 ADC.The AD7708/AD7718 filter is a low-pass, Sinc3 or (sinx/x)3As shown in the block diagram, the Sinc3 filter outputs alter-nately contain +VOS and –VOS, where VOS is the respectivechannel offset. This offset is removed by performing a runningaverage of two. This average by two means that the settling timeto any change in programming of the ADC will be twice thenormal conversion time, while an asynchronous step change onthe analog input will not be fully reflected until the third subse-quent output.tSETTLE=2fADC=2×tADCThe allowable range for SF is 13 to 255 with a default of 69(45H). The corresponding conversion rates, conversion times,and settling times are shown in Table I. Note that the conver-sion time increases by 0.732 ms for each increment in SF.fCHOPfINfMODfCHOPfADCANALOG INPUTMUXBUFPGA?-?MOD0XOR(1?8 ? SF(33 ?(8 ? SF )1?2DIGITALOUTPUTSINC 3 FILTERAIN + VOSAIN – VOSFigure 4.ADC Channel Block Diagram with CHOP EnabledREV. 0–15–
半导体传感器AD7794BRUZ中文规格书 - 图文
