PCI Express Endpoint Connectivity
[Figure1-2, callout 13]
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5gigatransfers per second (GT/s) for a Gen1 application and 5.0GT/s for a Gen2 application. The PCIe transmit and receive signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7series FPGAs GTX transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX485T-2FFG1761C FPGA (-2 speed grade) included with the VC707 board supports up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and the _N net is connected to pin AB7. The PCI Express clock circuit is shown in Figure1-14.
X-Ref Target - Figure 1-14P1PCI ExpressEight-LaneEdge connectorOEGNDREFCLK+REFCLK-GNDA12A13A14A15GNDPCIE_CLK_Q0_C_PPCIE_CLK_Q0_C_NC5440.01μF 25VX7RPCIE_CLK_Q0_PPCIE_CLK_Q0_NC5450.01μF 25VX7RUG885_c1_14_020612Figure 1-14:PCI Express Clock
PCIe lane width/size is selected through jumper J49 (Figure1-15). The default lane size selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15PCIE_PRSNT_X1PCIE_PRSNT_X4PCIE_PRSNT_X8135J49246PCIE_PRSNT_BUG885_c1_15_020612Figure 1-15:PCI Express Lane Size Select Jumper J49
Table1-12 lists the PCIe edge connector connections at P1.
Table 1-12:
Net NamePCIE_RX0_PPCIE_RX0_NPCIE_RX1_PPCIE_RX1_NPCIE_RX2_PPCIE_RX2_NPCIE_RX3_P
PCIe Edge Connector Connections GTX Quad 115
FPGA (U1)PCIe Edge Connector (P1)
PinPinName
Y4Y3AA6AA5AB4AB3AC6
B14B15B19B20B23B24B27
PETp0PETn0PETp1PETn1PETp2PETn2PETp3
Function
Integrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pair
FHG1761
Placement
GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y8
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKVC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
drivers must be installed on the host PC prior to establishing communications with the VC707 board.
The USB Connector Pin Assignments and Signal Definitions between J17 and U44 are listed in Table1-19.
Table 1-19:
USB Connector J17 Pin Assignments and Signal Definitions
Net Name
Description
CP2103GM (U44)Pin7843229
NameREGINVBUSD–D+GND1CNR_GND
USB Connector (J17)Pin1234
NameVBUSD_ND_PGND
USB_UART_VBUSUSB_D_NUSB_D_PUSB_UART_GND
+5V VBUS Powered
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
Table1-20 shows the USB connections between the FPGA and the UART.
Table 1-20:
FPGA to UART Connections
FPGA (U1)
PinAR34AT32AU36AU33
FunctionRTSCTSTXRX
DirectionOutputInputOutputInput
IOSTANDARDLVCMOS18LVCMOS18LVCMOS18LVCMOS18
Schematic Net
NameUSB_CTSUSB_RTSUSB_RXUSB_TX
CP2013 Device (U12)
Pin22232425
FunctionCTSRTSRXDTXD
DirectionInputOutputInputOutput
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref20].
HDMI Video Output
[Figure1-2, callout 18]
The VC707 board provides a High-Definition Multimedia Interface (HDMI?) video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60Hz YCbCr and RGB video modes through 36-bit input data mapping.The VC707 board supports the following HDMI device interfaces:??????
36 data lines
Independent VSYNC, HSYNCSingle-ended input CLKInterrupt Out Pin to FPGAI2CSPDIF
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
The VC707 board I2C bus topology is shown in Figure1-22.
X-Ref Target - Figure 1-22U1FPGABank 15(2.5V)U52PCA954812C 1-to-8Bus SwitchCH0 - USER_CLK_SDL/SCLCH1 - FMC1_HPC_IIC_SDA/SCLCH2 - FMC2_HPC_IIC_SDA/SCLCH3 - EEPROM_IIC_SDA/SCLCH4 - SFP_IIC_SDA/SCLCH5 - IIC_SDA/SCL_HDMICH6 - IIC_SDA/SCL_DDR3CH7 - SI5324_SDA/SCLUG855_C1_22_021012IIC_SDA/SCL_MAINFigure 1-22:
I2C Bus Topology
User applications that communicate with devices on one of the downstream I2C buses must first set up a path to the desired bus through the U52 bus switch at I2C address 0x74 (0b1110100). Table1-24 lists the address for each bus.Table 1-24:
I2C Bus Addresses
I2C Switch Position
NA01234567
I2C Address
0b11101000b10111010bXXXXX000bXXXXX000b10101000b10100000b0111001
0b1010000, 0b00110000b1101000
I2C Device
PCA9548Si570 ClockFMC1 HPCFMC2 HPCM24C08 EEPROMSFP ModuleADV7512 HDMIDDR3 SODIMMSi5324 Clock
Notes:
1.Use the PCA9458 (U52) at I2C address 0x74 (0b1110100) to setup the path to these buses.
Information about the PCA9548 is available on the TI Semiconductor website [Ref25].
Caution!The PCA9548 U52 RESET_B pin 24 is connected to the FPGA U1 bank 15 pin AY42
via level-shifter U70. The FPGA pin AY42 LVCMOS18 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to U52.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Feature Descriptions
Status LEDs
[Figure1-2, callout 21]
Table1-25 defines the status LEDs. For user controlled LEDs see User I/O.
Table 1-25:ReferenceDesignatorDS11DS11DS12DS12DS13DS13DS14DS10DS1DS16DS17DS18
Status LEDs
Signal Name
PHY_LED_RXPHY_LED_LINK1000PHY_LED_TXPHY_LED_LINK100PHY_LED_DUPLEXPHY_LED_LINK10PWRCTL1_VCC4A_PGFPGA_DONEFPGA_INIT_BVCC12_P_INPWRCTL_PWRGOODLINEAR_POWER_GOOD
ColorGREENGREENGREENGREENGREENGREENGREENGREENGREEN/REDGREENGREENGREEN
Ethernet PHY RX
Ethernet Link Speed is 1000 Mb/sEthernet PHY TX
Ethernet Link Speed is 100 Mb/sEthernet Link is Half-duplexEthernet Link Speed is 10 Mb/sFMC1 HPC Power GoodFPGA Configured SuccessfullyGREEN: FPGA Initialization Successful,RED: FPGA Initialization in Progress12V Power ON
UCD9248 Power Controllers (U42, U43, U64)Power Good
TPS51200 Power Good (U23)
Description
User I/O
[Figure1-2, callout 22 - 26]
The VC707 board provides the following user and general purpose I/O capabilities:??
Eight user LEDs (callout 22)???????
????
GPIO_LED_[7-0]: DS9, DS8, DS7, DS6, DS5, DS4, DS3, DS2CPU_RESET: SW8
GPIO_SW_[NESWC]: SW3, SW4, SW5, SW7, SW6GPIO_DIP_SW[7-0]: SW2
ROTARY_PUSH, ROTARY_INCA, ROTARY_INCB: SW10USER_SMA_GPIO_P, USER_SMA_GPIO_N: J33, J34
If the display is unmounted, connector J23 pins are available as 7 independent GPIOs. TheLCD connector J23 details are shown in the LCD Character Display (16 x 2) section.Reset switch and five user pushbuttons (callout 23)
8-position user DIP Switch (callout 24)
User rotary switch (callout 25, hidden beneath the LCD)User SMA (callout 26)
2 line x 16 character LCD character display (callout 19)
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
FPGA可编程逻辑器件芯片XQR4013XL-3CB228M中文规格书 - 图文
