Device Command Codes
The system CPU provides control of all in-system READ, WRITE, and ERASE operationsof the device via the system bus. The device manages all block-erase and word-programalgorithms.
Device commands are written to the CUI to control all device operations. The CUI doesnot occupy an addressable memory location; it is the mechanism through which thedevice is controlled.
Note: For a dual device, all setup commands should be re-issued to the device when adifferent die is selected.
Table 10: Command Codes and Definitions
ModeReadDevice ModeRead arrayRead status registerCode0xFF0x70DescriptionPlaces the device in read array mode. Array data is output on DQ[15:0].Places the device in read status register mode. The device enters thismode after a PROGRAM or ERASE command is issued. Status registerdata is output on DQ[7:0].Places device in read device identifier mode. Subsequent reads outputmanufacturer/device codes, configuration register data, block lock sta-tus, or protection register data on DQ[15:0].Places the device in read CFI mode. Subsequent reads output CFI infor-mation on DQ[7:0].The device sets status register error bits. The clear status register com-mand is used to clear the SR error bits.First cycle of a 2-cycle programming command; prepares the CUI for aWRITE operation. On the next write cycle, the address and data arelatched and the device executes the programming algorithm at the ad-dressed location. During PROGRAM operations, the device respondsonly to READ STATUS REGISTER and PROGRAM SUSPEND commands.CE# or OE# must be toggled to update the status register in asynchro-nous read. CE# or ADV# must be toggled to update the status registerdata for synchronous non-array reads. The READ ARRAY commandmust be issued to read array data after programming has finished.This command loads a variable number of words up to the buffer sizeof 512 words onto the program buffer.The CONFIRM command is issued after the data streaming for writinginto the buffer is completed. The device then performs the bufferedprogram algorithm, writing the data from the buffer to the memoryarray.First cycle of a two-cycle command; initiates buffered enhanced factoryprogram mode (BEFP). The CUI then waits for the BEFP CONFIRM com-mand, 0xD0, that initiates the BEFP algorithm. All other commands areignored when BEFP mode begins.If the previous command was BEFP SETUP (0x80), the CUI latches theaddress and data, and prepares the device for BEFP mode.Read device ID orread configurationregisterRead CFIClear status registerWriteWord program setup0x900x980x500x40Buffered programBuffered programconfirm0xE80xD0BEFP setup0x80BEFP confirm0xD0PDF: 09005aef84566799
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Device Command Codes
Table 10: Command Codes and Definitions (Continued)
ModeEraseDevice ModeBlock erase setupCode0x20DescriptionFirst cycle of a two-cycle command; prepares the CUI for a BLOCKERASE operation. The device performs the erase algorithm on theblock addressed by the ERASE CONFIRM command. If the next com-mand is not the ERASE CONFIRM (0xD0) command, the CUI sets statusregister bits SR4 and SR5, and places the device in read status registermode.If the first command was BLOCK ERASE SETUP (0x20), the CUI latchesthe address and data, and the device erases the addressed block. Dur-ing BLOCK ERASE operations, the device responds only to READ STATUSREGISTER and ERASE SUSPEND commands. CE# or OE# must be toggledto update the status register in asynchronous read. CE# or ADV# mustbe toggled to update the status register data for synchronous non-ar-ray reads.This command issued to any device address initiates a suspend of thecurrently-executing program or BLOCK ERASE operation. The statusregister indicates successful suspend operation by setting either SR2(program suspended) or SR6 (erase suspended), along with SR7 (ready).The device remains in the suspend mode regardless of control signalstates (except for RST# asserted).This command issued to any device address resumes the suspendedPROGRAM or BLOCK ERASE operation.First cycle of a two-cycle command; prepares the CUI for block lock con-figuration changes. If the next command is not BLOCK LOCK (0x01),BLOCK UNLOCK (0xD0), or BLOCK LOCK DOWN (0x2F), the CUI sets sta-tus register bits SR5 and SR4, indicating a command sequence error.If the previous command was BLOCK LOCK SETUP (0x60), the addressedblock is locked.If the previous command was BLOCK LOCK SETUP (0x60), the addressedblock is unlocked. If the addressed block is in a lock down state, the op-eration has no effect.If the previous command was BLOCK LOCK SETUP (0x60), the addressedblock is locked down.First cycle of a two-cycle command; prepares the device for a OTP REG-ISTER or LOCK REGISTER PROGRAM operation. The second cycle latchesthe register address and data, and starts the programming algorithmto program data the OTP array.First cycle of a two-cycle command; prepares the CUI for device readconfiguration. If the SET READ CONFIGURATION REGISTER command(0x03) is not the next command, the CUI sets status register bits SR4and SR5, indicating a command sequence error.If the previous command was READ CONFIGURATION REGISTER SETUP(0x60), the CUI latches the address and writes A[16:1] to the read con-figuration register for Easy BGA and TSOP, A[15:0] for QUAD+. Follow-ing a CONFIGURE READ CONFIGURATION REGISTER command, subse-quent READ operations access array data.Block erase confirm0xD0SuspendProgram or erasesuspend0xB0Suspend resumeProtectionBlock lock setup0xD00x60Block lockBlock unlock0x010xD0Block lock downOTP register or lockregister program set-upConfigurationRead configurationregister setup0x2F0xC00x60Read configurationregister0x03PDF: 09005aef84566799
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Status Register
sequence error occurs during an ERASE SUSPEND, the status register contains the com-mand sequence error status (SR[7,5,4] set). When the ERASE operation resumes and fin-ishes, possible errors during the operation cannot be detected via the status register be-cause it contains the previous error status.
3.When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-ISTER 50h) or a RESET command must be issued with a 15μs delay.
Clear Status Register
The CLEAR STATUS REGISTER command clears the status register. It functions inde-pendently of VPP. The device sets and clears SR[7,6,2], but it sets bits SR[5:3,1] withoutclearing them. The status register should be cleared before starting a command se-quence to avoid any ambiguity. A device reset also clears the status register.
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Configuration Register
Configuration Register
Read Configuration Register
The read configuration register (RCR) is a 16-bit read/write register used to select busread mode (synchronous or asynchronous) and to configure device synchronous burstread characteristics. To modify RCR settings, use the CONFIGURE READ CONFIGURA-TION REGISTER command. RCR contents can be examined using the READ DEVICEIDENTIFIER command and then reading from offset 0x05. On power-up or exit from re-set, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-low.
Note: Reading the configuration register is a nonarray READ operation. When the oper-ation occurs in asynchronous page mode, only the first data is valid, and all subsequentdata are undefined. When the operation occurs in synchronous burst mode, the sameword of data requested will be output on successive clock edges until the burst lengthrequirements are satisfied.
Table 17: Read Configuration Register
Bits15NameRead mode (RM)Settings/Description0 = Synchronous burst mode read1 = Asynchronous page mode read (default)0000 = Code 0 (reserved)0001 = Code 1 (reserved)0010 = Code 20011 = Code 30100 = Code 40101 = Code 50110 = Code 60111 = Code 71000 = Code 81001 = Code 91010 = Code 101011 = Code111100 = Code 121101 = Code 131110 = Code 141111 = Code 15 (default)14:11Latency count(LC[3:0])1098765:432:0WAIT polarity (WP)Reserved (R)WAIT delay (WD)Burst sequence (BS)Clock edge (CE)Reserved (R)Burst wrap (BW)0 = WAIT signal is active LOW (default)1 = WAIT signal is active HIGHDefault 0, Nonchangeable0 = WAIT de-asserted with valid data1 = WAIT de-asserted one data cycle before valid data (default)Default 0, Nonchangeable0 = Falling edge1 = Rising edge (default)Default 0, Nonchangeable0 = Wrap; Burst accesses wrap within burst length set by BL[2:0]1 = No Wrap; Burst accesses do not wrap within burst length (default)011 = 16-word burst111 = Continuous burst (default)(Other bit settings are reserved)Burst length (BL[2:0])001 = 4-word burst010 = 8-word burstRead Mode
The read mode (RM) bit selects synchronous burst mode or asynchronous page modeoperation for the device. When the RM bit is set, asynchronous page mode is selected(default). When RM is cleared, synchronous burst mode is selected.
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Configuration Register
Latency Count
The latency count (LC) bits tell the device how many clock cycles must elapse from therising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until thefirst valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-mine this value. The First Access Latency Count figure shows the data output latency fordifferent LC settings.
Figure 13: First Access Latency Count
CLK [C]Address [A]ValidAddressADV# [V]Code 0 (ReservedDQ[15:0] [D/Q]ValidOutputCode 1(Reserved)Code 2DQ[15:0] [D/Q]Code 3ValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutput)ValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputValidOutputDQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]Code 4DQ[15:0] [D/Q]Code 5DQ[15:0] [D/Q]Code 6DQ[15:0] [D/Q]Code 7Note:1.First Access Latency Count Calculation:
?1 / CLK frequency = CLK period (ns)
?n x (CLK period) ≥ tAVQV (ns) – tCHQV (ns)?Latency Count = n
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MEMORY存储芯片NAND256W3A2BN6E中文规格书 - 图文
