DS302 (v3.7) September 9, 2009
00Product Specification
Virtex-4 FPGA Electrical Characteristics
Virtex?-4 FPGAs are available in -12, -11, and -10 speedgrades, with -12 having the highest performance.
Virtex-4 FPGA DC and AC characteristics are specified forboth commercial and industrial grades. Except the operat-ing temperature range or unless otherwise noted, all the DCand AC electrical parameters are the same for a particularspeed grade (that is, the timing characteristics of a -10speed grade industrial device are the same as for a -10speed grade commercial device). However, only selectedspeed grades and/or devices might be available in theindustrial range.
All supply voltage and junction temperature specificationsare representative of worst-case conditions. The parame-ters included are common to popular designs and typicalapplications.
This Virtex-4 FPGA Data Sheet is part of an overall set ofdocumentation on the Virtex-4 family of FPGAs that is avail-able on the Xilinx website:?????????
Virtex-4 Family Overview, DS112Virtex-4 FPGA User Guide, UG070
Virtex-4 FPGA Configuration Guide, UG071
XtremeDSP for Virtex-4 FPGAs User Guide, UG073Virtex-4 FPGA Packaging and Pinout Specification,UG075
Virtex-4 FPGA PCB Designer’s Guide, UG072
Virtex-4 RocketIO? Multi-Gigabit Transceiver UserGuide, UG076
Virtex-4 FPGA Embedded Tri-Mode Ethernet MACUser Guide, UG074
PowerPC? 405 Processor Block Reference Guide,UG018
All specifications are subject to change without notice.
Virtex-4 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
VCCINTVCCAUXVCCOVBATTVREF
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage
I/O input voltage relative to GND (all user and dedicated I/Os)
–0.5 to 1.32–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.3 to 3.75–0.75 to 4.05–0.95 to 4.4
(Commercial Temperature)
Units
VVVVVV
VIN
I/O input voltage relative to GND
(restricted to maximum of 100 user I/Os)(3,4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
–0.85 to 4.3
(Industrial Temperature)
V
–0.75 to VCCO+0.5
±100±200
VmAmA
IIN
Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpowered
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 50: Miscellaneous Timing Parameters
Speed Grade
Symbol
Time Required to Achieve LOCKT_LOCK_DLL_240T_LOCK_DLL_120_240T_LOCK_DLL_60_120T_LOCK_DLL_50_60T_LOCK_DLL_40_50T_LOCK_DLL_30_40T_LOCK_DLL_24_30T_LOCK_DLL_30T_LOCK_FX_MAX
T_LOCK_DLL_FINE_SHIFTFine Phase ShiftingFINE_SHIFT_RANGE_MSFINE_SHIFT_RANGE_MRDelay Lines
DCM_TAP_MS_MINDCM_TAP_MS_MAXDCM_TAP_MR_MINDCM_TAP_MR_MAXInput Signal RequirementsDCM_RESET(4)
DCM_INPUT_CLOCK_STOP
Minimum duration that RST must be held assertedMaximum duration that RST can be held asserted(5)Maximum duration that CLKIN and CLKFB can be stopped(6,7)
Tap delay resolution (Min) in maximum speed modeTap delay resolution (Max) in maximum speed modeTap delay resolution (Min) in maximum range modeTap delay resolution (Max) in maximum range mode
5401060
5401060
5401060
pspspsps
Absolute shifting range in maximum speed modeAbsolute shifting range in maximum range mode
710
710
710
nsns
DLL output – Frequency range > 240MHz (2)DLL output – Frequency range 120 - 240MHz (1,2)DLL output – Frequency range 60 - 120MHz (1,2)DLL output – Frequency range 50 - 60MHz(1,2)DLL output – Frequency range 40 - 50MHz (1,2)DLL output – Frequency range 30 - 40MHz (1,2)DLL output – Frequency range 24 - 30MHz(1,2)DLL output – Frequency range < 30MHz (2)DFS outputs(3)
Multiplication factor for DLL lock time with Fine Shift
206322532550090012501250102
206322532550090012501250102
206322532550090012501250102
μs μs μs μs μs μs μs μs ms
Description-12-11-10Units
20010100
20010100
20010100
mssecms
Notes:
1.For boundary frequencies, choose the higher delay.
2.DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.3.DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.4.CLKIN must be present and stable during the DCM_RESET.
5.This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support
of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
6.For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped
clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to supportlonger durations of stopped clocks.
7.For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 51: Frequency Synthesis
Attribute
CLKFX_MULTIPLYCLKFX_DIVIDE
Min
21
Max
3232
Table 52: DCM Switching Characteristics
Symbol
TDMCCK_PSEN/TDMCKC_PSEN
TDMCCK_PSINCDEC/TDMCKC_PSINCDECTDMCKO_PSDONE
PSEN Setup/HoldPSINCDEC Setup/HoldClock to out of PSDONE
Description
Speed Grade-12
0.930.000.930.000.60
-11
0.930.000.930.000.60
-10
1.070.001.070.000.69
Units
nsnsns
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 62: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade-12
–0.450.97
-11
–0.451.08
-10
–0.441.17
Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIOTPSCS/TPHCS
Setup/Hold of I/O clock across multiple clock regions
ns
Pin-to-Pin Clock-to-Out Using BUFIOTICKOFCS
Clock-to-Out of I/O clock across multiple clock regions
4.10
4.54
5.02
ns
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Current Virtex-4 Production Devices
Table64 summarizes the current production LX and SX device stepping.Table 64: Current LX and SX Production Devices
LX/SX Device SteppingExample Ordering CodeDevice steppings shipped when ordered per Example Ordering Code
Step 1
XC4VLX60-10FF672CStep 1 or Step 2?
Capability Improvements(1)
The DFS macro is nolonger needed
Step 2
XC4VLX60-10FF672CS2Step 2???
TCONFIG requirement is removed
DCM_RESET requirement is removed
DCM_INPUT_CLOCK_STOP requirement is
removed by a macro (automatically inserted by ISEsoftware)
CONFIG STEPPING parameter (must be set in UCF file)Minimum Software RequiredMinimum Speed Specification Required.
“1”
ISE 7.1i SP41.58
“2”
ISE 7.1i SP41.58
DS302 (v3.7) September 9, 2009Product Specification
FPGA可编程逻辑器件芯片XC4VLX40-11FFG668C中文规格书 - 图文
