Chapter 7:GTX Receiver (RX)
PRBS Detection
Overview
The GTX receiver includes a built-in PRBS checker. This checker can be set to check for one of three industry-standard PRBS patterns. The checker is self-synchronizing and works on the incoming data before comma alignment or decoding. This function can be used to test the signal integrity of the channel.
Ports and Attributes
Table7-25 defines the PRBS detection ports.
Table 7-25:
Port
INTDATAWIDTHPRBSCNTRESET0PRBSCNTRESET1
PRBS Detection Ports
DirInIn
Clock DomainAsyncRXUSRCLK2
Description
Specifies the width of the internal datapath for the entire GTX_DUAL tile.Resets the PRBS error counter.
PRBSCNTRESET is applied synchronously. Receiver test pattern checker control:00: Disable PRBS checkers
In
RXUSRCLK2
01: Enable 27-1 PRBS checker10: Enable 223-1 PRBS checker11: Enable 231-1 PRBS checker
RXPRBSERR goes High when the number of errors in PRBS testing
RXUSRCLK2exceeds the value set by the PRBS_ERR_THRESHOLD attribute.
RXENPRBSTST0[1:0]RXENPRBSTST1[1:0]
RXPRBSERR0RXPRBSERR1
Out
Table7-26 defines the PRBS detection attributes.
Table 7-26:
PRBS Detection Attributes
Type
Description
Sets the error threshold for the PRBS checker. If PRBS testing is enabled, a counter counts the number of errors. If the number of errors exceeds the value of PRBS_ERR_THRESHOLD, the output RXPRBSERR goes High. This attribute is set as a 32-bit hex value.
Attribute
PRBS_ERR_THRESHOLD0PRBS_ERR_THRESHOLD1
32-bit Hex
Description
To use the built-in PRBS checker, RXENPRBSTST is set to match the PRBS pattern being sent to the receiver. The RXENPRBSTST entry in Table7-25 shows the available settings.When the PRBS checker is running, it attempts to find the selected PRBS pattern in the incoming data. When it finds the pattern, it can detect PRBS errors by comparing the incoming pattern with the expected pattern.
The checker counts the number of errors it sees and compares it with
PRBS_ERR_THRESHOLD. When the error count exceeds the threshold, RXPRBSERR is asserted. Asserting PRBSCNTRESET clears RXPRBSERR. GTXRESET, RXCDRRESET, and RXRESET also reset the count.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Configurable RX Elastic Buffer and Phase Alignment
To limit the set of commas that trigger RXCHARISCOMMA to K28.1, K28.5, and K28.7, DEC_VALID_COMMA_ONLY is set to TRUE. This setting is typically used for Ethernet-based applications. RXCHARISCOMMA does not depend on MCOMMA_10B_VALUE or PCOMMA_10B_VALUE.
RX Running Disparity
The 8B/10B decoder uses a running disparity system to balance the number of 1s and 0s transmitted. The 8B/10B decoder tracks the running disparity of incoming data to detect errors. Monitor the RXRUNDISP port to see the current running disparity.
Disparity Errors and Not-in-Table Errors
The decoder drives RXDISPERR High when RXDATA arrives with the wrong disparity. In addition to disparity errors, the 8B/10B decoder detects 20-bit out-of-table error codes. The decoder drives the RXNOTINTABLE port High when RXDATA is not a valid 8B/10B character.
Figure7-22 shows a waveform with a few error bytes arriving on RXDATA and the RXNOTINTABLE and RXDISPERR ports indicating the error.
X-Ref Target - Figure 7-22RXUSRCLK2GoodDataDispError Out ofTableBothErrorsGoodData RXDATARXDISPERRRXNOTINTABLEUG198_c7_21_040507Figure 7-22:RX Data with 8B/10B Errors
Configurable RX Elastic Buffer and Phase Alignment
Overview
The GTX RX datapath has two internal parallel clock domains used in the PCS: the PMA parallel clock domain (XCLK) and the RXUSRCLK domain. To receive data, the PMA parallel rate must be sufficiently close to the RXUSRCLK rate, and all phase differences between the two domains must be resolved. Figure7-23 shows the two parallel clock domains, XCLK and RXUSRCLK.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2V8000-6BF957I中文规格书
