Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width increases, the number of address lines along with the number of addressable memory locations decreases. Using the permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown in Table14.
Table 14:Port Aspect Ratios for Port A or B
DI/DO Bus Width(w – p Bits)
12481632
DIP/DOP Bus Width (p Bits)
000124
Total Data Path Width (w Bits)
12491836
ADDR Bus Width
(r Bits)
14131211109
No. of Addressable Block RAM Locations (n)Capacity (Bits)
16,3848,1924,0962,0481,024512
16,38416,38416,38418,43218,43218,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of Figure15, Figure16, and Figure17 during which WE is Low.
X-Ref Target - Figure 15CLKWEDIADDRDOXXXX11112222XXXXaabbccdd0000MEM(aa)11112222MEM(dd)ENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_14_091410Figure 15:Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure15 during which WE is High.Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure16 during which WE is High.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
CLKWEDIADDRDOENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_15_030403XXXX11112222XXXXaabbccdd0000MEM(aa)old MEM(bb)old MEM(cc)MEM(dd)Figure 16:Waveforms of Block RAM Data Operations with READ_FIRST Selected
Choosing a third attribute called NO_CHANGE puts the DO outputs in a latched state when asserting WE. Under this condition, the DO outputs will retain the data driven just before WE was asserted. NO_CHANGE timing is shown in the portion of Figure17 during which WE is High.
X-Ref Target - Figure 17CLKWEDIADDRDOENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_16_030403XXXX11112222XXXXaabbccdd0000MEM(aa)MEM(dd)Figure 17:Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. This section provides an introduction to multipliers. For further details, refer to the chapter entitled “Using Embedded Multipliers” in UG331.
The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned). One such multiplier is matched to each block RAM on the die. The close physical proximity of the two ensures efficient data handling. Cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. The multiplier is placed in a design using one of two primitives: an asynchronous version called MULT18X18 and a version with a register called MULT18X18S, as shown in Figure18. The signals for these primitives are defined in Table15.
The CORE Generator system produces multipliers based on these primitives that can be configured to suit a wide range of requirements.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 18A[17:0]A[17:0]B[17:0]MULT18X18P[35:0]B[17:0]CLKCERST(a)Asynchronous 18-bit MultiplierMULT18X18SP[35:0](b)18-bit Multiplier with RegisterDS099-2_17_091510Figure 18:Embedded Multiplier Primitives
Table 15:Embedded Multiplier Primitives Descriptions
Signal NameA[17:0]B[17:0]P[35:0]CLKCERSTNotes:
1.
The control signals CLK, CE and RST have the option of inverted polarity.
DirectionInputInputOutputInput(1)Input(1)Input(1)
Function
Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK.
Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK.
The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the MULT18X18S primitive, an enabled rising CLK edge updates the P bus.
CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input, when enabled by CE, updates the output register that drives the P bus.
CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input enables the CLK signal to update the P bus.
RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register on an enabled, rising CLK edge, forcing the P bus to all zeroes.
Digital Clock Manager (DCM)
Spartan-3 devices provide flexible, complete control over clock frequency, phase shift and skew through the use of the DCM feature. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature and voltage. This section provides a fundamental description of the DCM. For further information, refer to the chapter entitled “Using Digital Clock Managers” in UG331.
Each member of the Spartan-3 family has four DCMs, except the smallest, the XC3S50, which has two DCMs. The DCMs are located at the ends of the outermost Block RAM column(s). See Figure1, page3. The Digital Clock Manager is placed in a design as the “DCM” primitive.The DCM supports three major functions: ?
Clock-skew Elimination: Clock skew describes the extent to which clock signals may, under normal circumstances,deviate from zero-phase alignment. It occurs when slight differences in path delays cause the clock signal to arrive atdifferent points on the die at different times. This clock skew can increase set-up and hold time requirements as well asclock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. TheDCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal thatis fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively cancels out clockdistribution delays that may lie in the signal path leading from the clock output of the DCM to its feedback input.Frequency Synthesis: Provided with an input clock signal, the DCM can generate a wide range of different outputclock frequencies. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal byany of several different factors.
?
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S200-5FGG456I中文规格书 - 图文
