FPGA可编程逻辑器件芯片EP1S20F780C5中文规格书 - 图文

For the packing of two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab).

In the case of implementing two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4×2crossbar switch (two 4-to-1 multiplexers with

common inputs and unique select lines) can be implemented in one ALM, as shown in Figure2–8. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture.

Figure2–8.4 × 2 Crossbar Switch Example

4 × 2 Crossbar Switchsel0[1..0]inputainputbinputcinputdout1sel1[1..0]datae1dataf1Six-InputLUT(Function1)out0dataf0datae0dataadatabdatacdatadImplementation in 1 ALMSix-InputLUT(Function0)combout0combout1In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs. The QuartusII Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the QuartusII software automatically utilizes the full potential of the StratixII ALM. The QuartusII Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments.

Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see Figure2–9). If

Stratix II Device Handbook, Volume 1

I/O Structure

Table2–15 shows the possible settings for the I/O standards with drive strength control.

Table2–15.Programmable Drive StrengthNote(1)

I/O Standard

3.3-V LVTTL3.3-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class IIHSTL-18 Class IHSTL-18 Class IIHSTL-15 Class IHSTL-15 Class IINote to Table2–15:(1)

The QuartusII software default current setting is the maximum setting for each I/O standard.

IOH / IOL Current Strength Setting (mA) for Column

I/O Pins

24, 20, 16, 12, 8, 424, 20, 16, 12, 8, 4

16, 12, 8, 412, 10, 8, 6, 4, 2

8, 6, 4, 212, 824, 20, 1612, 10, 8, 6, 420, 18, 16, 812, 10, 8, 6, 420, 18, 1612, 10, 8, 6, 420, 18, 16

IOH / IOL Current Strength Setting (mA) for Row I/O

Pins

12, 8, 48, 412, 8, 48, 6, 4, 24, 212, 81610, 8, 6, 4

-12, 10, 8, 6, 4

-8, 6, 4-

Open-Drain Output

StratixII devices provide an optional open-drain (equivalent to an open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write-enable signals) that can be asserted by any of several devices.

Bus Hold

Each StratixII device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its

last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

Stratix II Device Handbook, Volume 1

StratixII Architecture

Each I/O bank has its own VCCIO pins. A single device can support 1.5-,1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different VCCIO level independently. Each bank also has dedicated VREF pins to support the voltage-referenced standards (such as SSTL-2). The PLL banks utilize the adjacent VREF group when voltage-referenced standards are implemented. For example, if an SSTL input is

implemented in PLL bank10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.

I/O pins that reside in PLL banks 9 through 12 are powered by the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The EP2S60F484,

EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are powered by the VCCIO3 pin, and any I/O pins that reside in bank 12 are powered by the VCCIO8 pin.

Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one VREF voltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.

On-Chip Termination

StratixII devices provide differential (for the LVDS or HyperTransport technology I/O standard), series, and parallel on-chip termination to reduce reflections and maintain signal integrity. On-chip termination simplifies board design by minimizing the number of external

termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections.StratixII devices provide four types of termination:

■■■■

Differential termination (RD)

Series termination (RS) without calibrationSeries termination (RS) with calibrationParallel termination (RT) with calibration

Stratix II Device Handbook, Volume 1

StratixII Architecture

Stratix II Device Handbook, Volume 1

I/O Structure

Table2–18 summarizes StratixII MultiVolt I/O support.

Table2–18.StratixII MultiVolt I/O SupportNote(1)VCCIO (V)

1.21.51.82.53.3(1)(2)

Input Signal (V)

1.2

(4)(4)(4)(4)(4)

Output Signal (V)

3.3

v (2)v (2)v (2)vv

1.5

v (2)vv

1.8

v (2)vv

2.5

v (2)v (2)v (2)vv

1.2

v (4)v (3)v (3)v (3)v (3)

1.5

vv (3)v (3)v (3)

1.82.53.35.0

vv (3)v (3)

vv (3)

v

v

Notes to Table2–18:

To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTLand LVCMOS input levels to overdrive input buffer option in the QuartusII software.

The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL

maximum and VOH minimum voltages do not violate the applicable StratixII VIL maximum and VIH minimum voltage specifications.

Although VCCIO specifies the voltage necessary for the StratixII device to drive out, a receiving device powered at a different level can still interface with the StratixII device if it has inputs that tolerate the VCCIO value.StratixII devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. StratixII devices support 1.2-V HSTL.

(3)(4)

The TDO and nCEO pins are powered by VCCIO of the bank that they reside in. TDO is in I/O bank 4 and nCEO is in I/O bank 7.

Ideally, the VCC supplies for the I/O buffers of any two connected pins are at the same voltage level. This may not always be possible depending on the VCCIO level of TDO and nCEO pins on master devices and the

configuration voltage level chosen by VCCSEL on slave devices. Master and slave devices can be in any position in the chain. Master indicates that it is driving out TDO or nCEO to a slave device.

For multi-device passive configuration schemes, the nCEO pin of the master device drives the nCE pin of the slave device. The VCCSEL pin on the slave device selects which input buffer is used for nCE. When VCCSEL is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When VCCSEL is logic low it selects the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the VCCIO of the nCEO bank in a master device match the VCCSEL settings for the nCE input buffer of the slave device it is connected to, but that may not be possible depending on the application. Table2–19 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations.

Stratix II Device Handbook, Volume 1