Internal ECC and Spare Area Mapping for ECC
Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the sparearea. The metadata II area, which consists of two bytes (x8) and one word (x16), is notECC protected. During the busy time for PROGRAM operations, internal ECC generatesparity bits when error detection is complete.
During READ operations the device executes the internal ECC engine (5-bit detectionand 4-bit error correction). When the READ operaton is complete, read status bit 0 mustbe checked to determine whether errors larger than four bits have occurred.
Following the READ STATUS command, the device must be returned to read mode byissuing the 00h command.
Limitations of internal ECC include the spare area, defined in the figures below, andECC parity areas that cannot be written to. Each ECC user area (referred to as main andspare) must be written within one partial-page program so that the NAND device cancalculate the proper ECC parity. The number of partial-page programs within a pagecannot exceed four.
Figure 80: Spare Area Mapping (x8)
Max ByteMin Byte AddressAddressECC ProtectedAreaDescription 1FFh000hYesMain 0User data 3FFh200hYesMain 1User data 5FFh400hYesMain 2User data 7FFh600hYesMain 3User data 801h800hNoReserved 803h802hNoUser metadata II 807h804hYesSpare 0User metadata I 80Fh808hYesSpare 0ECC for main/spare 0 811h810hNoReserved 813h812hNoUser metadata II 817h814hYesSpare 1User metadata I 81Fh818hYesSpare 1ECC for main/spare 1 821h820hNoReserved 823h822hNoUser metadata II 827h824hYesSpare 2User metadata I 82Fh828hYesSpare 2ECC for main/spare 2 831h830hNoUser data 833h832hNoUser metadata II 837h834hYesSpare 3User metadata I 83Fh838hYesSpare 3ECC for main/spare 3 Bad BlockInformation 2 bytesECC Parity8 bytesUser Data(Metadata)6 bytesPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Electrical Specifications – AC Characteristics and Operating
Conditions
Table 31: AC Characteristics: Normal Operation (3.3V)
Note 1 applies to allParameterALE to RE# delayCE# access timeCE# HIGH to output High-ZCLE to RE# delayCE# HIGH to output holdOutput High-Z to RE# LOWREAD cycle timeRE# access timeRE# HIGH hold timeRE# HIGH to output holdRE# HIGH to WE# LOWRE# HIGH to output High-ZRE# LOW to output holdRE# pulse widthReady to RE# LOWReset time (READ/PROGRAM/ERASE)WE# HIGH to busyWE# HIGH to RE# LOWNotes:
SymboltARtCEAtCHZtCLRtCOHtIRtRCtREAtREHtRHOHtRHWtRHZtRLOHtRPtRRtRSTtWBtWHRMin10––1015020–715100–51020––60Max–2550––––16–––100–––5/10/500100–UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsμsnsnsNotes2231.AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2.Transition is measured ±200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3.The first time the RESET (FFh) command is issued while the device is idle, the device will
go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5μs.
Table 32: AC Characteristics: Normal Operation (1.8V)
Note 1 applies to allParameterALE to RE# delayCE# access timeCE# HIGH to output High-ZCLE to RE# delayCE# HIGH to output holdOutput High-Z to RE# LOWREAD cycle timeRE# access timeRE# HIGH hold timeRE# HIGH to output holdRE# HIGH to WE# LOWPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
SymboltARtCEAtCHZtCLRtCOHtIRtRCtREAtREHtRHOHtRHWMin10––1015025–1015100Max–2550––––22–––UnitnsnsnsnsnsnsnsnsnsnsnsNotes24Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Electrical Specifications – AC Characteristics and Operating
Conditions
PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Electrical Specifications – Program/Erase Characteristics
Electrical Specifications – Program/Erase Characteristics
Table 33: Program/Erase Characteristics
ParameterNumber of partial-page programsBLOCK ERASE operation timeBusy time for PROGRAM CACHE operationCache read busy timeBusy time for SET FEATURES and GET FEATURES operationsBusy time for OTP DATA PROGRAM operation if OTP is pro-tectedBusy time for PROGRAM/ERASE on locked blocksPROGRAM PAGE operation time, internal ECC disabledPROGRAM PAGE operation time, internal ECC enabledData transfer from Flash array to data register, internal ECCdisabledData transfer from Flash array to data register, internal ECCenabledBusy time for OTP DATA PROGRAM operation if OTP is pro-tected, internal ECC enabledBusy time for TWO-PLANE PROGRAM PAGE or TWO-PLANEBLOCK ERASE operationNotes:
SymbolNOPtBERStCBSYtRCBSYtFEATtOBSYtLBSYtPROGtPROG_ECCtRtR_ECCtOBSY_ECCtDBSYTyp–0.733–––200220–45–0.5Max436002513036006002570501UnitcyclesmsμsμsμsμsμsμsμsμsμsμsμsNotes1283, 86, 73, 51.Four total partial-page programs to the same page. If ECC is enabled, then the device is
limited to one partial-page program per ECC user area, not exceeding four partial-pageprograms per page.
2.tCBSY MAX time depends on timing between internal program completion and data-in.3.Parameters are with internal ECC enabled.
4.Typical is nominal voltage and room temperature.
5.Typical tR_ECC is under typical process corner, nominal voltage, and at room tempera-ture.
6.Data transfer from Flash array to data register with internal ECC disabled.
7.AC characteristics may need to be relaxed if I/O drive strength is not set to full.
8.Typical program time is defined as the time within which more than 50% of the pages
are programmed at nominal voltage and room temperature.
PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Asynchronous Interface Timing Diagrams
Asynchronous Interface Timing Diagrams
Figure 82: RESET Operation
CLECE#tWBWE#tRSTR/B#I/O[7:0]FFhRESETcommandFigure 83: READ STATUS Cycle
tCLRCLEtCLStCLHCE#tCStWPWE#tCHtCEAtWHRRE#tRHZtDS I/O[7:0]70htDHtIRtREAtRHOHStatusoutputtRPtCOHtCHZDon’t CarePDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
MEMORY存储芯片MT29F4G08ABAEAWPE中文规格书 - 图文
