Using Both Corner PLLs in Arria II GX Devices
You can use both corner PLLs to drive DPA-disabled channels simultaneously. Both corner PLLs can drive cross-banks.
You can use a corner PLL to drive all the transmitter channels and you can use the other corner PLL to drive all DPA-disabled receiver channels in the same I/O bank.Both corner PLLs can drive duplex channels in the same I/O bank if the channels driven by each PLL are not interleaved. No separation is necessary between the group of channels driven by both corner PLLs.
Setting Up an LVDS Transmitter or Receiver Channel
The ALTLVDS megafunction offers you the ease of setting up an LVDS transmitter or receiver channel. You can control the settings of SERDES and DPA circuitry in the ALTLVDS megafunction. When you instantiate an ALTLVDS megafunction, the PLL is instantiated automatically and you can set the parameters of the PLL. This megafunction simplifies the clocking setup for the LVDS transmitter or receiver channels. However, the drawback is reduced flexibility when using the PLL. The ALTLVDS megafunction provides an option for implementing the LVDS
transmitter or receiver interfaces with external PLLs. With this option enabled, you can control the PLL settings, such as dynamically reconfiguring the PLLs to support different data rates, dynamic phase shift, and other settings. You also must instantiate an ALTPLL megafunction to generate the various clock and load enable signals.
fFor more information about how to control the PLL, SERDES, and DPA block settings,
and detailed descriptions of the LVDS transmitter and receiver interface signals, refer to the SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide.fFor more information about the ALTPLL megafunction, refer to the Phase Locked-Loops
(ALTPLL) Megafunction User Guide.
Document Revision History
Table8–9 lists the revision history for this chapter.
Table8–9.Document Revision History(Part 1 of 2)
DateJuly 2012December 2011June 2011
Version4.34.24.1
Updated Figure8–23.
■■■■
Changes Made
Updated “Differential Receiver” section.Minor text edits.Updated Figure8–2.Minor text edits.
Added Arria II GZ device information.Updated Table8–3 and Table8–4.Updated Figure8–2.
Updated for the QuartusII software version 10.1 release:
December 2010
4.0
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 9:Configuration, Design Security, and Remote System Upgrades in ArriaII DevicesFast Passive Parallel Configuration
Figure9–2.Multi-Device FPP Configuration Using an External Host
MemoryADDRDATA[7..0] (2) (1) (1)10 kΩ10 kΩ10 kΩ (1)(3)10 kΩ Arria II Device 1MSEL[n..0]CONF_DONEnSTATUS Arria II Device 2MSEL[n..0]CONF_DONEnSTATUS(3)External Host(MAX II Device orMicroprocessor)nCEGNDDATA[7..0]nCONFIGDCLKnCEOnCEDATA[7..0]nCONFIGDCLKnCEON.C.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 9:Configuration, Design Security, and Remote System Upgrades in ArriaII DevicesAS and Fast AS Configuration (Serial Configuration Devices)
Guidelines for Connecting Serial Configuration Device to ArriaII Devices on an AS Interface
For single- and multi-device AS configurations, the board trace length and loading between the supported serial configuration device and the ArriaII devices must follow the recommendations listed in Table9–11.
Table9–11.Maximum Trace Length and Loading for the AS Configuration in ArriaII Devices
ArriaII Device AS Pins
DCLKDATA[0]nCSOASDOMaximum Board Trace Length from the ArriaII Device to the Serial Configuration Device (Inches)
10101010
Maximum Board Load (pF)
15303030
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 9:Configuration, Design Security, and Remote System Upgrades in ArriaII DevicesJTAG Configuration
JTAG Configuration
JTAG has developed a specification for boundary-scan testing. This boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. The BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. You can also use JTAG circuitry to shift configuration data into the device. The QuartusII software automatically generates .sofs that you can use for JTAG configuration with a download cable in the QuartusII software programmer.
fFor more information about JTAG boundary-scan testing and commands available
using ArriaII devices, refer to the following documents:
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JTAG Boundary-Scan Testing in ArriaII Devices chapterProgramming Support for Jam STAPL Language
ArriaII devices are designed such that JTAG instructions have precedence over any device configuration modes. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. For example, if you attempt JTAG configuration of ArriaII devices during PS configuration, PS configuration is terminated and JTAG configuration begins.
1
You cannot use the ArriaII decompression or design security features if you are configuring your ArriaII device using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors (typically 25k?). All the JTAG pins are powered by the VCCIO power supply of I/O bank 8C for ArriaIIGX devices and 2.5-V/3.0-V VCCPD power supply for ArriaIIGZ devices. All the JTAG pins support only the LVTTL I/O standard.
All user I/O pins are tri-stated during JTAG configuration. Table9–13 lists the function of each JTAG pin.
fFor more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the JTAG Boundary-Scan Testing in ArriaII Devices chapter.
Table9–13.JTAG Pins Signals(Part 1 of 2)Pin NameTDIPin TypeTest data inputTest data output
Description
Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCK. If the JTAG interface is not required on your board, you can disable the JTAG circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data. Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. If the JTAG interface is not required on your board, you can disable the JTAG circuitry by leaving this pin unconnected.
1
TDOArria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 9:Configuration, Design Security, and Remote System Upgrades in ArriaII Devices
JTAG Configuration
Table9–13.JTAG Pins Signals(Part 2 of 2)Pin Name
Pin Type
Description
Input pin that provides the control signal to determine the transitions of the TAP controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the rising edge of TCK. Transitions within the state machine occur on the falling edge of TCK after the signal is applied to TMS. If the JTAG interface is not required on your board, you can disable the JTAG circuitry by connecting this pin to logic high.
Clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at the falling edge. If the JTAG interface is not required on your board, you can disable the JTAG circuitry by connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is optional according to the IEEE Std. 1149.1 standard. If the JTAG interface is not required on your board, you can disable the JTAG circuitry by connecting the TRST pin to GND. Onek? pull-up resistor to VCCPD if you do not use the TRST pin.
TMSTest mode select
TCKTest clock inputTest reset input (optional)
TRST (1)
Note to Table9–13:
(1)The TRST pin is only available for ArriaIIGZ devices.
During JTAG configuration, you can download data to the device on the PCB through the USB-Blaster, ByteBlasterII, EthernetBlaster, or EthernetBlasterII download cable. Figure9–16 shows the JTAG configuration of a single ArriaII device.
Figure9–16.JTAG Configuration of a Single Device Using a Download Cable
VCCIO/VCCPD
(2) VCCIO/VCCPGM(1) VCCIO/VCCPGM(1) 10 kΩGNDN.C.10 kΩ (3)VCCIO/VCCPD(2) (3)Arria II DevicenCE (4)nCE0TCKTDOTMSTDI(5)(5)(5)nSTATUSCONF_DONEnCONFIGMSEL[n..0]DCLKDownload Cable 10-Pin Male Header(JTAG Mode) (Top View)Pin 1VCCIO/VCCPD(2)GNDVIO (6)1 kΩGNDGNDNotes to Figure9–16:
(1)Connect the pull-up resistors to the VCCIO power supply of I/O bank 3C for ArriaIIGX devices and to VCCPGM (1.8-V, 2.5-V or 3.0-V) power supply
for Arria II GZ devices.(2)Connect the pull-up resistor to the same supply voltage, VCCIO for ArriaIIGX devices or VCCPD for ArriaIIGZ devices as the USB-Blaster,
ByteBlasterII, EthernetBlaster, or EthernetBlasterII cable.(3)The resistor value can vary from 1 K? to 10 K?.
(4)You must connect nCE to GND or drive it low for successful JTAG configuration.
(5)Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect nCONFIG to
VCCIO for ArriaIIGX device, VCCPGM for ArriaIIGZ device, and MSEL to GND. Pull DCLK either high or low, whichever is convenient on your board.(6)In the USB-Blaster and ByteBlasterII cables, this pin is a no connect.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX95DF25I3中文规格书 - 图文
