READ 81h 83h 85h 87h 89h 8Bh 8Dh 8Fh 91h
WRITE BIT 7 BIT 6 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h
CH 12/24 0 0 0 WP TCS
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
Seconds Minutes Hour Date Month
0 0 DS
Day Year 0 0 DS RS
BIT 0 RANGE 00–59
00–59 1–12/0–23 1–31 1–12 1–7 00–99 — —
10 Seconds 10 Minutes
10
0 Hour
AM/PM 0 10 Date
10
0 0
Month
0 0 0 10 Year 0 0 0 TCS TCS TCS
0
RS
CLOCK BURST
BFh
BEh
RAM
C1h C3h C5h ...FDh
C0h C2h C4h ...FCh
00-FFh00-FFh00-FFh..
.
00-FFh
RAM BURST
FFh
FEh
Figure 5. Programmable Trickle Charger
TRICKLE CHARGE REGISTER (90h write, 91h read)Bit 7TCS3Bit 6TCS2Bit 5TCS1Bit 4TCS0Bit 3DS1Bit 2DS0Bit 1ROUT1Bit 0ROUT0TCS0-3 = TRICKLE CHARGER SELECTDS0-1 = DIODE SELECTROUT0-1 = RESISTOR SELECT1 0F 16 SELECTNOTE: ONLY 1010b ENABLES CHARGER1 OF 2SELECT1 OF 3SELECTR1VCC22K?R24k?R38k?VCC1DS1302 Trickle-Charge Timekeeping Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C Soldering Temperature (surface mount)………………………………………………..…….See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER
Supply Voltage VCC1, VCC2 Logic 1 Input Logic 0 Input
SYMBOL VCC1, VCC2 VIH VIL
VCC = 2.0V VCC = 5V
CONDITIONS (Notes 2, 10) (Note 2) (Note 2)
MIN 2.0 2.0 -0.3-0.3
TYP 3.3
MAX 5.5 VCC + 0.3 +0.3+0.8
UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER
Input Leakage I/O Leakage
Logic 1 Output (IOH = -0.4mA) Logic 1 Output (IOH = -1.0mA) Logic 0 Output (IOL = 1.5mA) Logic 0 Output (IOL = 4.0mA) Active Supply Current (Oscillator Enabled) Timekeeping Current (Oscillator Enabled) Standby Current (Oscillator Disabled)
Active Supply Current (Oscillator Enabled) Timekeeping Current (Oscillator Enabled) Standby Current (Oscillator Disabled)
Trickle-Charge Resistors Trickle-Charge Diode Voltage Drop
ILI ILO VOH VOL ICC1A ICC1T ICC1S ICC2A ICC2T ICC2S R1 R2 R3 VTD
VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V IND
VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V
2 4 8 0.7
SYMBOL
CONDITIONS (Notes 5, 13) (Notes 5, 13) (Note 2) (Note 2) CH = 0
(Notes 4, 11) CH = 0
(Notes 3, 11,13) CH = 1
(Notes 9, 11, 13) CH = 0
(Notes 4, 12) CH = 0
(Notes 3, 12) CH = 1
(Notes 9, 12)
0.2 0.45 1 1 5
1.6 2.4
0.4 0.4 0.4 1.2 0.3 1 100 100 200 0.425 1.28 25.3 81 25 80
k?
MIN
TYP 85 85
MAX 500 500
UNITS μA μA V V mA μA nA mA μA μA
V
DS1302 Trickle-Charge Timekeeping Chip
CE AND CLOCK CONTROL
Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer.
A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 4 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri-stated upon each rising edge of SCLK. Data is output starting with bit 0.
BURST MODE
Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second.
The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed.
DS1302 Trickle-Charge Timekeeping Chip
PIN DESCRIPTION
PIN
NAME
FUNCTION
Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Ground
Input. CE signal must be asserted high during a read or a write. This pin has an internal 40k? (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40k? (typ) pulldown resistor to ground.
Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40k? (typ) pulldown resistor to ground.
Low-Power Operation in Single Supply and Battery-Operated Systems and Low-Power Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery.
1 VCC2
2 X1
3 4 5
X2 GND CE
6 7
I/O SCLK
8 VCC1
MEMORY存储芯片DS1302ZN-1中文规格书 - 图文
