Configuration Details
Configuration Pins
Certain pins are dedicated to configuration (Table5-1), while others are dual-purpose (Table5-3). Dual-purpose pins serve both as configuration pins and as user I/Os after configuration. Dedicated configuration pins retain their function after configuration.Configuration constraints can be selected when generating the Spartan?-6 device bitstream. Certain configuration operations can be affected by these constraints. For a description of the available constraints, see the software constraints guide.
Table 5-1:
Spartan-6 FPGA Dedicated Configuration Pins
Type(1)
Description
Pin NameDONE
Bidirectional, Active High signal with programmable pull-up indicating configuration is complete.Open-Drain, 0 = FPGA not configuredor Active1 = FPGA configured
Refer to the BitGen section of UG628, Command Line Tools User Guide, for software settings.
InputInput
Active Low signal with programmable pull-up, asynchronous full-chip reset.
PROGRAM_B(2, 3)
TDI
Test Data In. This pin is the serial input to all JTAG instruction and data registers.
The state of the TAP controller and the current instruction determine the register that is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic High to the system if the pin is not driven. TDI is applied into the JTAG registers on the rising edge of TCK.
Test Data Out. This pin is the serial output for all JTAG instruction and data registers. The state of the TAP controller and the current instruction determine the register (instruction or data) that feeds TDO for a specific operation. TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output.
Test Mode Select. This pin determines the sequence of states through the JTAG TAP controller on the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the pin is not driven.
Test Clock. This pin is the JTAG Test Clock. TCK sequences the TAP controller and the JTAG registers.
Suspend Mode. Used to put the FPGA into suspend mode.
The SUSPEND pin should be Low during power up and configuration. If the Suspend feature is not used, the SUSPEND pin must be connected to ground.
TDOOutput
TMSInput
TCKSUSPEND(3)
InputInput
VFSVBATT
InputInput
Voltage source for eFUSE programming.(4)
Battery supply voltage for AES encryption key storage in SRAM.(4)
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
If it is a known-vendor command, the SPI read command needs to be loaded to GENERAL2.
In case of SPI, the general register contains an 8-bit command plus a 24-bit address. See Table5-42.Table 5-42:
SPI General Register Example
gen1[15:0]addr[15:0]
gen2[15:0]rd_cmd[7:0], addr[23:16]
BPI has a 26-bit address (there are 6 don’t care bits). See Table5-43.Table 5-43:
BPI General Register Example
gen1[15:0]addr[15:0]
gen2[15:0]xxxxxx, address[25:16]
MODE Register
The MODE register contains the mode setting (twobits for bus width, threebits for mode, and eightbits for vsel), which can be used for the reboot. The default is the original pin setting.
This register is cleared in the same way as General registers, that is they can only be cleared by bus_reset0 but NOT by reboot_rst (bus_reset = bus_reset || reboot_rst). See Table5-44.Table 5-44:
NameRESERVEDRESERVEDNEW_MODE
MODE Registers Description
Bits151413
Reserved.Reserved.
0: Physical mode, ignore bit[10:0] (default).1: Bitstream mode, use bit[10:0], required for MultiBoot and Fallback.The buswidth setting to reboot.SPI:00: by 101: by 210: by 4
Mode setting required for MultiBoot and Fallback. Enabled by NEW_MODE.bit [10]: Reservedbit [9]: BOOTMODE <1>bit [8]: BOOTMODE <0>
Description
Default000
BUSWIDTH12:1100 (SPI by1)
BOOTMODE10:8001
BOOTVSEL7:0The vsel setting to reboot.Read only.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Readback Command Sequences
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
h.Write two dummy words to the device to flush the packet buffer.
The MSB of all configuration packets sent through the CFG_IN register must be sent first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.8.
Shift the CFG_OUT instruction into the JTAG Instruction Register through the
Shift-DR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shiftedwhile moving the TAP controller out of the SHIFT-IR state.Shift frame data from the FDRO register through the Shift-DR state.
9.
10.Reset the TAP controller.
Table 6-6:Shutdown Readback Command Sequence (JTAG)Step
Description
Clock five 1s on TMS to bring the device to the TLR state.1
Move into the RTI state.Move into the Select-IR state.Move into the Shift-IR state.
Shift the first five bits of the CFG_IN instruction, LSB first.2
Shift the MSB of the CFG_IN instruction while exiting Shift-IR.
Move into the SELECT-DR state.Move into the SHIFT-DR state.
Set and HoldTDI
XXXX
# of Clocks (TCK)TMS
10100110
51225122
00101
0XXa: 0xFFFF
b: 0xAA99b: 0x5566c: 0x30A1d: 0x0007e: 0x2000f: 0x2000
0XX
Shift configuration packets into the CFG_IN data register, MSB first.3
Shift the LSB of the last configuration packet while exiting SHIFT-DR.
Move into the SELECT-IR state.Move into the SHIFT-IR state.
Shift the first five bits of the JSHUTDOWN instruction, LSB first.
Shift the MSB of the JSHUTDOWN instruction while exiting SHIFT-IR.
Move into the RTI state; remain there for 24TCK cycles.5
Move into the Select-IR state.Move into the Shift-IR state.
0111
11001010
132512422
01101
0XXX
4
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2S30-6CS144I中文规格书 - 图文
