ParameterInput capacitance: CK, CK#Delta input capacitance: CK, CK#Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODTDelta input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE,ODTInput/output capacitance: DQ, DQS, DM, NFDelta input/output capacitance: DQ, DQS, DM, NFSymbolMinMaxUnitsNotesCCKCDCKCICDICIOCDIO1.0–1.0–2.5–2.00.252.00.254.00.5pFpFpFpFpFpF12, 31, 42, 31, 52, 3PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2007 Micron Technology, Inc. All rights reserved.
1GbDDR2.pdf – Rev. Y 02/14 ENPDF: 09005aef8565148aTable 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1VAC Characteristics-187E-25E-25-3E-3-37E-5EParameterSymbolMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnitsNotesDQ output accesstAC–350350–400400–400400–450450–450450–500500–600600ps19time from CK/CK#DQS–DQ skew,tDQSQ–175–200–200–240–240–300–350ps26, 27DQS to last DQvalid, per group,per accessDQ hold from nexttQHS–250–300–300–340–340–400–450ps28tuODQS strobe-aDQ–DQS hold, DQStQHMIN = tHP - tQHSps26, 27,taDto first DQ not val-MAX = n/a28idCK/CK# to DQ, DQStHZMIN = n/aps19, 21,High-ZMAX = tAC (MAX)29CK/CK# to DQtLZ2MIN = 2 × tAC (MIN)ps19, 21,Low-ZMAX = tAC (MAX)22Data valid outputDVWMIN = tQH - tDQSQns26, 27windowMAX = n/aDQ and DM inputtDSb0–50–50–100–100–100–150–ps26, 30,setup time to DQS31DQ and DM inputtDHb75–125–125–175–175–225–275–ps26, 30,nhold time to DQS31I-taDQ and DM inputDSa200–250–250–300–300–350–400–ps26, 30,taDsetup time to DQS31DQ and DM inputtDHa200–250–250–300–300–350–400–ps26, 30,hold time to DQS31DQ and DM inputtDIPWMIN = 0.35 × tCKtCK18, 32pulse widthMAX = n/aAC Timing Operating Specifications1Gb: x4, x8, x16 DDR2 SDRAMPreliminary1GbDDR2.pdf – Rev. Y 02/14 ENPDF: 09005aef8565148aTable 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1VAC Characteristics-187E-25E-25-3E-3-37E-5EParameterSymbolMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnitsNotesInput setup timetISb125–175–175–200–200–250–350–ps31, 33Input hold timetIHb200–250–250–275–275–375–475–ps31, 33Input setup timetISa325–375–375–400–400–500–600–ps31, 33Input hold timetIHa325–375–375–400–400–500–600–ps31, 33Input pulse widthtIPW0.6–0.6–0.6–0.6–0.6–0.6–0.6–tCK18, 32ACTIVATE-to-tRC54–55–55–54–55–55–55–ns18, 34,ACTIVATE delay,51same bankstsACTIVATE-to-READRCD13.125–12.5–15–12–15–15–15–ns18eror WRITE delayddtAACTIVATE-to-RAS4070K4070K4070K4070K4070K4070K4070Kns18, 34, dPRECHARGE delay35nat PRECHARGE periodRP13.125–12.5–15–12–15–15–15–ns18, 36dntaPRE-<1GbRPA13.125–12.5–15–12–15–15–15–ns18, 36mCHARGEtmRPA15–15–17.5 15 18 18.75 20 ns18, 36oALL period≥1GbCACTIVATEx4, x8tRRD7.5–7.5–7.5–7.5–7.5–7.5–7.5–ns18, 37-to-x16tRRD10–10–10–10–10–10–10–ns18, 37ACTIVATEdelaydifferentbank4-bankx4, x8tFAW35–35–35–37.5–37.5–37.5–37.5–ns18, 38activatex16tFAW45–45–45–50–50–50–50–ns18, 38period(≥1Gb)AC Timing Operating Specifications1Gb: x4, x8, x16 DDR2 SDRAMPreliminaryPreliminary
1Gb: x4, x8, x16 DDR2 SDRAM
Power and Ground Clamp Characteristics
Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only balls: Address balls,bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.
Table 25: Input Clamp Characteristics
Voltage Across Clamp (V)0.00.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.8Minimum Power Clamp Current(mA)0.00.00.00.00.00.00.00.00.11.02.54.76.89.111.013.516.018.221.0Minimum Ground Clamp Current(mA)0.00.00.00.00.00.00.00.00.11.02.54.76.89.111.013.516.018.221.0Figure 21: Input Clamp Characteristics
25Minimum Clamp Current (mA) 20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8Voltage Across Clamp (V)
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Preliminary
1Gb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification
Table 26: Address and Control Balls
Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, and ODTSpecificationParameterMaximum peak amplitude allowed for overshoot area(see Figure 22)Maximum peak amplitude allowed for undershoot area(see Figure 23)Maximum overshoot area above VDD (see Figure 22)Maximum undershoot area below VSS (see Figure 23)-187E0.50V0.50V0.5 Vns0.5 Vns-25/-25E0.50V0.50V0.66 Vns0.66 Vns-3/-3E0.50V0.50V0.80 Vns0.80 Vns-37E0.50V0.50V1.00 Vns1.00 Vns-5E0.50V0.50V1.33 Vns1.33 VnsTable 27: Clock, Data, Strobe, and Mask Balls
Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, and LDMSpecificationParameterMaximum peak amplitude allowed for overshoot area(see Figure 22)Maximum peak amplitude allowed for undershoot area(see Figure 23)Maximum overshoot area above VDDQ (see Figure 22)Maximum undershoot area below VSSQ (see Figure 23)-187E0.50V0.50V0.19 Vns0.19 Vns-25/-25E0.50V0.50V0.23 Vns0.23 Vns-3/-3E0.50V0.50V0.23 Vns0.23 Vns-37E0.50V0.50V0.28 Vns0.28 Vns-5E0.50V0.50V0.38 Vns0.38 VnsFigure 22: Overshoot
Maximum amplitude
Volts (V)Overshoot areaVDD/VDDQVSS/VSSQ
Time (ns)
Figure 23: Undershoot
VSS/VSSQVolts (V)Undershoot areaMaximum amplitudeTime (ns)
Table 28: AC Input Test Conditions
ParameterInput setup timing measurement reference level addressballs, bank address balls, CS#, RAS#, CAS#, WE#, ODT,DM, UDM, LDM, and CKEPDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
SymbolVRSMinMaxUnitsNotes1, 2, 3, 4See Note 2
MEMORY存储芯片MT29F8G08ADBDAH4-ITD中文规格书 - 图文
