Signal NameDALIGN
TypeStatus
Access
Only available through the SelectMAP interface during an ABORT. (See “Configuration Abort Sequence Description,” page 49.)
DescriptionIndicates whether device is synchronized.
Check Device ID (Step 5)
Steps1DevicePower-Up2ClearConfigurationMemory3Sample ModePins4Synchronization5Device IDCheck6LoadConfigurationData7CRC Check8StartupSequenceStartBitstreamLoadingFinishug071_07_122105Figure 1-7:Check Device ID (Step 5)
Once the device is synchronized, a device ID check must pass before the configuration data frames can be loaded. This prevents an attempted configuration with a bitstream that is formatted for a different device.
For example, the device ID check should prevent an XC4VLX15 from being configured with an XC4VLX80 bitstream.
The device ID check is built into the bitstream, making this step transparent to most designers. Figure1-7 shows the relative position of the device ID check, Table1-6 shows the Virtex-4 device IDs, and Table1-7 shows the signals relating to the device ID check. The device ID check is performed through commands in the bitstream to the configuration logic, not through the JTAG IDCODE register in this case.Table 1-6:Virtex-4 Device ID Codes
DeviceXC4VLX15XC4VLX25XC4VLX40XC4VLX60XC4VLX80XC4VLX100XC4VLX160
IDCODE016580930167C093016A4093016B4093016D80930170009301718093
XC4VFX100XC4VFX140
01EE409301F14093
XC4VSX25XC4VSX35XC4VSX55
0206809302088093020B0093
Device
IDCODE
DeviceXC4VFX12XC4VFX20XC4VFX40XC4VFX60
IDCODE01E5809301E6409301E8C093(1)01EB4093
Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017
Serial Configuration Interface
Clocking Serial Configuration Data
Figure2-2 shows how configuration data are clocked into Virtex-4 devices in Slave serial and Master serial modes.
PROGRAM_BINIT_BMaster CLK Begins Here(2)CCLKMaster DINMaster DOUT /Slave DIN DONEug071_016_073007BIT 0(1)BIT 1BIT nBIT n+1BIT n-64BIT n-63Data bits clocked on rising edge of CCLKFigure 2-2:Serial Daisy Chain Configuration Clocking Sequence
Notes relevant to Figure2-2:1.2.3.
In Figure2-2, bit 0 represents the MSB of the first byte. For example, if the first byte is0xAA (1010_1010), bit 0=1, bit 1=0, bit 2=1, etc.
For Master configuration mode, CCLK does not transition until after MODE pins aresampled, as indicated by the arrow.
CCLK can be free-running in Slave serial mode.
Master Serial Configuration
The Master serial mode is designed so that the FPGA can be configured from a Xilinx?serial configuration PROM, as shown in Figure2-3.
Xilinx Serial PROMDATACLKCERESET/OEM0(7)M1M2DINCCLK(7)DOUT(1)Virtex-4MasterSerial(2)PROGRAM_BDONEINIT_BPROGRAM_BUG071_12_073007Figure 2-3:Master Serial Mode Configuration
Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017
Chapter 2:Configuration Interfaces
Slave Serial Configuration
Slave serial configuration is typically used for devices in a serial daisy chain, or when configuring a single device from an external microprocessor or CPLD. Design
considerations are similar to Master serial configuration except for the direction of CCLK. A single device in Slave serial mode cannot simply be connected to a PROM, because CCLK is an input on both devices.
Serial Daisy Chains
Multiple Virtex-4 devices can be configured from a single configuration source by
arranging the devices in a serial daisy chain. In a serial daisy chain, devices receive their configuration data through their DIN pin, passing configuration data along to
downstream devices through their DOUT pin. The device closest to the configuration data source is considered the most upstream device, while the device furthest from the configuration data source is considered the most downstream device.
In a serial daisy chain, the configuration clock is typically provided by the most upstream device in Master serial mode. All other devices are set for Slave serial mode. Figure2-4 illustrates this configuration.
Alternatively, if a CPLD or microprocessor is used as a configuration controller, all devices can be set for Slave serial mode. (See “Configuring a Serial Daisy Chain with a Microprocessor or CPLD,” page 32.)
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
SelectMAP Configuration Interface
Table 2-4:Virtex-4 SelectMAP Configuration Interface PinsPin Name
M[2:0]CCLK
Type
InputInput and Output
Dedicated or Dual-Purpose
DedicatedDedicated
Description
MODE pins - determines configuration modeConfiguration clock source for all configuration modes except JTAG
Byte-wide (SelectMAP 8 bit) configuration and readback data bus, clocked on rising edge of
CCLK. D0 is the most-significant bit (MSB), D7 the least-significant bit (LSB). In SelectMAP 32 bit, configuring the data order is straight D0=LSB and D31=MSB.(1)
SelectMAP DataThree-State BidirectionalDual Purpose
Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017
SelectMAP Configuration Interface
Table 2-5:ABORT Status Word
Bit Number
D7
Status Bit NameCFGERR_B
Meaning
Configuration error (active Low)
0 = A configuration error has occurred.1 = No configuration error.Sync word received (active High)
D6
DALIGN
0 = No sync word received.
1 = Sync word received by interface logic.Readback in progress (active High)
D5
RIP
0 = No readback in progress.1 = A readback is in progress.ABORT in progress (active Low)
D4D3-D0
IN_ABORT_B
1111
0 = Abort is in progress.1 = No abort in progress.
Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017
FPGA可编程逻辑器件芯片XC4VLX60-10FF668C中文规格书 - 图文
