3.2：动态图形实验结果：
虽然拍的图片是静态的，但是从图中还可以看到图形变化的残影，效果很好。
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4：实验心得
兴趣是最好的老师，这是这次实验带给我最大的感触，当将枯燥无味的编程写代码变成了有趣的事情之后，动力就随之而来。从刚开始接触1602的时候，我的心里就十分希望能让那个屏幕显示出我自己想让它显示的各种奇奇怪怪的图像。于是我就去学了，于是我就去做了。当屏幕上出现我的名字，当小人真的奔跑起来的时候，我的内心是极其开心的。感谢PLD这门课让我接触了如此有意思的东西，同时也我也知道，我这个实验远远算不上创新，只是对我个人而言的新事物而已，PLD之路，任重而道远。
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5：附录
附录A：
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: //
// Create Date: 16:18:43 11/18/2015 // Design Name:
// Module Name: lcd1602 // Project Name: // Target Devices: // Tool versions: // Description: //
// Dependencies: //
// Revision:
// Revision 0.01 - File Created // Additional Comments: //
//////////////////////////////////////////////////////////////////////////////////
module lcd1602(clk,data,RS,RW,EN); input clk;
output[3:0] data;
output RS,RW,EN; /* RS=0--command;RS=1---data*/ reg[19:0]count=0; reg[19:0]count2=0; reg clk_500hz=0;
reg ready=1'b0,ready0=1'b0; reg[4:0]count1=5'b0000; reg [1:0] cnt;
/*************************************** **500HZ 时钟产生
****************************************/ always@(posedge clk) begin
if(count==50000) begin
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count<=0;
clk_500hz<=~clk_500hz; end else
count<=count+1; end
/**************************************** **上电延时20ms等待
*****************************************/
always@(posedge clk) begin
if(ready0==0) begin
if(count2==1000_000) begin
ready0<=1; end else
count2<=count2+1; end end
assign RW=0;
assign EN=clk_500hz; reg rs1=1'b0,rs2=1'b0; reg [3:0]data1=4'b0000; reg [3:0]data2=4'b0000; assign RS=rs1||rs2;
assign data=data1|data2;
reg [6:0]count3=6'b0000000; always@(posedge clk_500hz) begin
if((ready0==1)&&(ready==0)) begin
case(count3)
0:begin rs1<=0; data1<=4'h2; count3<=1; end //0x28 display mode
1:begin rs1<=0; data1<=4'h8; count3<=2; end //0x28 display mode
2:begin rs1<=0; data1<=4'h0; count3<=3; end //0x08 display off
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3:begin rs1<=0; data1<=4'hc; count3<=4; end //0x08 display off clear LCD clear LCD
[][1][]
//[][ ][]
[][][1]
//[][][ ]
4:begin rs1<=0; data1<=4'h0; count3<=5; end 5:begin rs1<=0; data1<=4'h6; count3<=6; end
6:begin rs1<=0; data1<=4'h0; count3<=7; end //0x01
7:begin rs1<=0; data1<=4'h1; count3<=8; end //0x01
8:begin rs1<=0; data1<=4'h4; count3<=9; end 9:begin rs1<=0; data1<=4'h0; count3<=10; end
10:begin rs1<=1;data1<=4'h1; count3<=11;end//第一行 11:begin rs1<=1;data1<=4'hf; count3<=12;end
12:begin rs1<=1;data1<=4'h0; count3<=13;end//第二行 13:begin rs1<=1;data1<=4'h4; count3<=14;end 14:begin rs1<=1;data1<=4'h0; count3<=15;end//3 15:begin rs1<=1;data1<=4'h8; count3<=16;end 16:begin rs1<=1;data1<=4'h1; count3<=17;end//4 17:begin rs1<=1;data1<=4'hf; count3<=18;end 18:begin rs1<=1;data1<=4'h1; count3<=19;end//5 19:begin rs1<=1;data1<=4'h1; count3<=20;end 20:begin rs1<=1;data1<=4'h1; count3<=21;end//6 21:begin rs1<=1;data1<=4'hf; count3<=22;end 22:begin rs1<=1;data1<=4'h1; count3<=23;end//7 23:begin rs1<=1;data1<=4'h1; count3<=39;end 39:begin rs1<=1;data1<=4'h1; count3<=40;end//8 40:begin rs1<=1;data1<=4'hf; count3<=24;end
24:begin rs1<=0; data1<=4'h4; count3<=25; end 25:begin rs1<=0; data1<=4'h8; count3<=26; end
26:begin rs1<=1;data1<=4'h0; count3<=27;end//第一行 27:begin rs1<=1;data1<=4'h8; count3<=28;end
28:begin rs1<=1;data1<=4'h0; count3<=29;end//第二行 29:begin rs1<=1;data1<=4'h4; count3<=30;end
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PLD与数字系统设计创新实验报告 - 图文
