Chapter 1:VC707 Evaluation Board Features
PCI Express Endpoint Connectivity
[Figure1-2, callout 13]
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5gigatransfers per second (GT/s) for a Gen1 application and 5.0GT/s for a Gen2 application. The PCIe transmit and receive signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7series FPGAs GTX transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX485T-2FFG1761C FPGA (-2 speed grade) included with the VC707 board supports up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and the _N net is connected to pin AB7. The PCI Express clock circuit is shown in Figure1-14.
X-Ref Target - Figure 1-14P1PCI ExpressEight-LaneEdge connectorOEGNDREFCLK+REFCLK-GNDA12A13A14A15GNDPCIE_CLK_Q0_C_PPCIE_CLK_Q0_C_NC5440.01μF 25VX7RPCIE_CLK_Q0_PPCIE_CLK_Q0_NC5450.01μF 25VX7RUG885_c1_14_020612Figure 1-14:PCI Express Clock
PCIe lane width/size is selected through jumper J49 (Figure1-15). The default lane size selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15PCIE_PRSNT_X1PCIE_PRSNT_X4PCIE_PRSNT_X8135J49246PCIE_PRSNT_BUG885_c1_15_020612Figure 1-15:PCI Express Lane Size Select Jumper J49
Table1-12 lists the PCIe edge connector connections at P1.
Table 1-12:
Net NamePCIE_RX0_PPCIE_RX0_NPCIE_RX1_PPCIE_RX1_NPCIE_RX2_PPCIE_RX2_NPCIE_RX3_P
PCIe Edge Connector Connections GTX Quad 115
FPGA (U1)PCIe Edge Connector (P1)
PinPinName
Y4Y3AA6AA5AB4AB3AC6
B14B15B19B20B23B24B27
PETp0PETn0PETp1PETn1PETp2PETn2PETp3
Function
Integrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pair
FHG1761
Placement
GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y8
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
drivers must be installed on the host PC prior to establishing communications with the VC707 board.
The USB Connector Pin Assignments and Signal Definitions between J17 and U44 are listed in Table1-19.
Table 1-19:
USB Connector J17 Pin Assignments and Signal Definitions
Net Name
Description
CP2103GM (U44)Pin7843229
NameREGINVBUSD–D+GND1CNR_GND
USB Connector (J17)Pin1234
NameVBUSD_ND_PGND
USB_UART_VBUSUSB_D_NUSB_D_PUSB_UART_GND
+5V VBUS Powered
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
Table1-20 shows the USB connections between the FPGA and the UART.
Table 1-20:
FPGA to UART Connections
FPGA (U1)
PinAR34AT32AU36AU33
FunctionRTSCTSTXRX
DirectionOutputInputOutputInput
IOSTANDARDLVCMOS18LVCMOS18LVCMOS18LVCMOS18
Schematic Net
NameUSB_CTSUSB_RTSUSB_RXUSB_TX
CP2013 Device (U12)
Pin22232425
FunctionCTSRTSRXDTXD
DirectionInputOutputInputOutput
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref20].
HDMI Video Output
[Figure1-2, callout 18]
The VC707 board provides a High-Definition Multimedia Interface (HDMI?) video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60Hz YCbCr and RGB video modes through 36-bit input data mapping.The VC707 board supports the following HDMI device interfaces:??????
36 data lines
Independent VSYNC, HSYNCSingle-ended input CLKInterrupt Out Pin to FPGAI2CSPDIF
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
Figure1-18 shows the HDMI codec circuit.
X-Ref Target - Figure 1-18VCC3V3R1042.43K1/10W1%HDMI_INTIIC_SCL_HDMIIIC_SDA_HDMIHDMI_VSYNCHDMI_HSYNCHDMI_CLKHDMI_HEAC_C_NHDMI_D35HDMI_D34HDMI_D33HDMI_D32HDMI_D31HDMI_D30HDMI_D29HDMI_D28HDMI_D27HDMI_D26HDMI_D25HDMI_D24HDMI_D23HDMI_D22HDMI_D21HDMI_D20HDMI_D19HDMI_D18HDMI_D17HDMI_D16HDMI_D15HDMI_D14HDMI_D13HDMI_D12HDMI_D11HDMI_D10HDMI_D9HDMI_D8HDMI_D7HDMI_D6HDMI_D5HDMI_D4HDMI_D3HDMI_D2HDMI_D1HDMI_D0HDMI_DEHDMI_SPDIFVADJR1062.43K1/10W1E38555629879305758596061626364656667686970717273747880818283848586878889909192939495969710345678911121314151617R433887GNDVCC2V5U41U48ADV7511INTPDSCLSDAVSYNCHSYNCCLKHPDD35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0DESPDIFDSD0DSD1DSD2DSD3DSD4DSD5DSD_CLKMCLKI2S0I2S1I2S2I2S3SCLKLRCLK212425HDMI_AVDDAVDD1AVDD2AVDD3293441HDMI_DVDDDVDD1DVDD2DVDD3DVDD4DVDD5767749191HDMI_DVDD_3VDVDD_3VBGVDDTX0_PTX0_NTX1_PTX1_NTX2_PTX2_NTXC_PTXC_NDDCSDADDCSCLHEAC_PHEAC_NCEC47HDMI_PLVDD2636354039434233325453525148HDMI_D0_PHDMI_D0_NHDMI_D1_PHDMI_D1_NHDMI_D2_PHDMI_D2_NHDMI_CLK_PHDMI_CLK_NHDMI_DDCSDAHDMI_DDCSCLHDMI_HEAC_PHDMI_HEAC_NHDMI_CECHDMI_PLVDDHDMI_AVDDCEC_CLKSPDIF_OUT5046HDMI_SPDIF_OUTC780.1UF25VX5R12GNDGNDSIT810212.00000 MHZ50PPM4VCC3OUTOE1GND21R1052.43K1/10W1%PVDD1PVDD2PVDD3To HDMIConnectorTo HDMIConnector28R_EXTGND1GND2GND3GND4GND5GND6GND7GND8GND9GND10GND1199100182022232731374475GNDUG855_c1_18_020612Figure 1-18:HDMI Codec Circuit
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Appendix A:Default Switch and Jumper Settings
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Appendix B:VITA 57.1 FMC Connector Pinouts
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2S200-4FG456I中文规格书 - 图文
