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FPGA可编程逻辑器件芯片EP2S30F484I3N中文规格书 - 图文

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1.StratixIII Device Data Sheet: DC and

Switching Characteristics

SIII52001-2.1

Electrical Characteristics

Operating Conditions

When Stratix?III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements discussed in this chapter. StratixIII devices are offered in both

commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speedgrades.

1

In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with “C” prefix and industrial with “I” prefix.

Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.

Table1–1.StratixIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)

SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVI

Parameter

Selectable core voltage power supplyI/O registers power supplyPLL digital power supplyPLL analog power supply

Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply

Differential clock input power supply (top and bottom I/O banks only)

Battery back-up power supply for design security volatile key registerDC Input voltage

Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5

Maximum1.651.651.653.753.753.93.93.93.753.754.0

UnitVVVVVVVVVVV

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing

Table1–85. EP3SL200 Column Pins output Timing Parameters (Part 4 of 7)

ParameterI/O Standard

Current StrengthFast ModelIndustrial

Commercial

C2VCCL=1.1V

C3VCCL=1.1V

C4VCCL=1.1V

VCCL=1.1V

C4L

VCCL=0.9V

I3VCCL=1.1V

I4VCCL=1.1V

VCCL=1.1V

I4LVCCL=0.9V

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Clock

GCLK

2mA

tco3.5851.7413.4541.6103.4091.5653.3981.5543.3631.5193.3591.5153.5651.7213.4421.5983.3891.5453.3691.5253.3821.5383.3851.5413.3671.523

3.9061.9793.7251.7983.6881.7613.6821.7553.6311.7043.6241.6973.8491.9223.7141.7873.6731.7463.6391.7123.6471.7203.6501.7233.6301.703

5.7402.6345.4962.3905.4162.3105.4102.3045.3622.2565.3412.2355.6942.5885.4752.3695.3992.2935.3602.2545.3682.2625.3722.2665.3502.244

5.9612.7355.7072.4815.6272.4015.6192.3935.5662.3405.5452.3195.9152.6895.6842.4585.6072.3815.5642.3385.5722.3465.5762.3505.5542.328

6.5283.0056.2572.7366.1772.6746.1682.6676.1072.6086.0872.6056.4712.9516.2312.7276.1572.6736.1072.6386.1152.6306.1192.6366.0972.609

6.3743.0016.1032.7306.0232.6506.0142.6415.9532.5805.9332.5606.3172.9446.0772.7046.0032.6305.9532.5805.9612.5885.9652.5925.9432.570

6.7876.1186.6896.5366.8883.2152.8653.1003.1222.9726.5165.8506.4026.2496.6012.8122.5972.8142.8362.6866.4365.7706.3196.1666.5182.7052.5172.7312.7532.6036.4275.7636.3126.1596.5112.6902.5102.7232.7452.5956.3665.7046.2476.0946.4462.6202.4512.6582.6802.5306.3465.6836.2256.0726.4242.5962.4302.6372.6592.5096.7306.0656.6236.4706.8223.1392.8123.0343.0562.9066.4905.8266.3746.2216.5732.7822.5732.7862.8082.6586.4165.7516.3026.1496.5012.6812.4982.7132.7352.5856.3665.7026.2456.0926.4442.6312.4492.6562.6782.5286.3745.7076.2506.0976.4492.6442.4542.6612.6832.5336.3785.7116.2546.1016.4532.6522.4582.6652.6872.5376.3565.6906.2326.0796.4312.6102.4372.6432.6652.515

GCLK

tco

PLLGCLK

tco

4mA

GCLK

tco

PLLGCLK

tco

6mA

1.5 V

GCLK

tco

PLLGCLK

tco

8mA

GCLK

tco

PLLGCLK

tco

10mA

GCLK

tco

PLLGCLK

tco

12mA

GCLK

tco

PLLGCLK

tco

2mA

GCLK

tco

PLLGCLK

tco

4mA

1.2 V

GCLK

tco

PLLGCLK

tco

6mA

GCLK

tco

PLLGCLK

tco

8mA

GCLK

tco

PLLGCLK

tco

8mA

GCLK

tco

PLLGCLK

tco

SSTL-2 CLASS I

10mA

GCLK

tco

PLLGCLK

tco

12mA

GCLK

tco

PLL

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

Table1–85. EP3SL200 Column Pins output Timing Parameters (Part 5 of 7)

ParameterI/O Standard

Current StrengthFast ModelIndustrial

Commercial

C2VCCL=1.1V

C3VCCL=1.1V

C4VCCL=1.1V

VCCL=1.1V

C4L

VCCL=0.9V

I3VCCL=1.1V

I4VCCL=1.1V

VCCL=1.1V

I4LVCCL=0.9V

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Clock

SSTL-2 CLASSII

GCLK

16mA

tco3.3621.5183.4001.5563.3811.5373.3821.5383.3651.5213.3621.5183.3621.5183.3611.5173.3921.5483.3771.5333.3641.5203.3641.5203.3601.516

3.6231.6963.6671.7403.6461.7193.6491.7223.6291.7023.6251.6983.6241.6973.6241.6973.6581.7313.6421.7153.6271.7003.6281.7013.6231.696

5.3352.2295.3912.2855.3692.2635.3772.2715.3522.2465.3482.2425.3362.2305.3442.2385.3842.2785.3702.2645.3502.2445.3512.2455.3442.238

5.5382.3125.5952.3695.5732.3475.5822.3565.5572.3315.5532.3275.5382.3125.5482.3225.5882.3625.5752.3495.5542.3285.5562.3305.5492.323

6.0802.6076.1382.6606.1162.6366.1262.6566.1012.6316.0962.6266.0802.6116.0922.6186.1302.6536.1182.6496.0982.6316.1012.6426.0932.634

5.9262.5535.9842.6115.9622.5895.9722.5995.9472.5745.9422.5695.9262.5535.9382.5655.9762.6035.9642.5915.9442.5715.9472.5745.9392.566

6.3395.6736.2146.0616.4132.5912.4202.6262.6482.4986.3975.7316.2746.1216.4732.6742.4782.6852.7072.5576.3755.7096.2516.0986.4502.6392.4562.6622.6842.5346.3855.7196.2626.1096.4612.6562.4662.6732.6952.5456.3605.6936.2366.0836.4352.6162.4402.6482.6702.5206.3555.6896.2326.0796.4312.6082.4362.6442.6662.5166.3395.6746.2156.0626.4142.5902.4212.6262.6482.4986.3515.6846.2286.0756.4272.5862.4312.6392.6612.5116.3895.7246.2666.1136.4652.6552.4712.6772.6992.5496.3775.7116.2556.1026.4542.6392.4582.6662.6882.5386.3575.6916.2346.0816.4332.6112.4382.6452.6672.5176.3605.6936.2376.0846.4362.6162.4402.6482.6702.5206.3525.6856.2296.0766.4282.6052.4322.6402.6622.512

GCLK

tco

PLLGCLK

tco

4mA

GCLK

tco

PLLGCLK

tco

6mA

GCLK

tco

PLLGCLK

tco

SSTL-18 CLASS I

8mA

GCLK

tco

PLLGCLK

tco

10mA

GCLK

tco

PLLGCLK

tco

12mA

GCLK

tco

PLLGCLK

tco

8mA

SSTL-18 CLASSII

GCLK

tco

PLLGCLK

tco

16mA

GCLK

tco

PLLGCLK

tco

4mA

GCLK

tco

PLLGCLK

tco

6mA

GCLK

tco

PLLGCLK

tco

SSTL-15 CLASS I

8mA

GCLK

tco

PLLGCLK

tco

10mA

GCLK

tco

PLLGCLK

tco

12mA

GCLK

tco

PLL

Stratix III Device Handbook, Volume 2

FPGA可编程逻辑器件芯片EP2S30F484I3N中文规格书 - 图文

1.StratixIIIDeviceDataSheet:DCandSwitchingCharacteristicsSIII52001-2.1ElectricalCharacteristicsOperatingConditionsWhenStratix?IIIdevicesareimplemented
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