Charge-trapping semiconductor memory device
申请(专利)号： KR20050085115
专利号： KR100646690B1 主分类号： H01L27/115
申请日： 2005-09-13 公开公告日： 2006-11-23
分类号： H01L27/115;
H01L21/8247; H01L21/8246 发明设计人： ??? ????? 申请国代码： KR
优先权： 20040914 US
10/940,414; 20040930 DE 102004047655.1
摘 要 附 图：
申请权利人： 公开国代码： KR 优先权国家： DE;
US
摘 要：
In accordance with the present invention, the memory cells in the main surface of the semiconductor substrate , preferably cylindrical recesses is formed by , a memory layer sequence on the gate electrode and the side wall and the first and the top and bottom source / drain region connected to the column for the second bit lines are provided. The word lines are disposed on the first and second bit lines coupled to the row of the gate electrode . Vertical transistor structure enables the minimum effective channel length easily and requires additional reduction of the cells . 主权项：
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Charge-trapping semiconductor memory device
