Chapter 1:StratixIII Device Family OverviewArchitecture Features
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For more information, refer to the Clock Networks and PLLs in StratixIII Devices chapter.
I/O Banks and I/O Structure
StratixIII devices contain up to 24 modular I/O banks, each of which contains 24, 32, 36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases device migration. The I/O banks contain circuitry to support external memory
interfaces at speeds up to 533MHz and high-speed differential I/O interfaces meeting up to 1.6Gbps performance. It also supports high-speed differential inputs and outputs running at speeds up to 800MHz.
StratixIII devices support a wide range of industry I/O standards, including
single-ended, voltage referenced single-ended, and differential I/O standards. The StratixIII I/O supports programmable bus hold, programmable pull-up resistor, programmable slew rate, programmable drive strength, programmable output delay control, and open-drain output. StratixIII devices also support on-chip series (RS) and on-chip parallel (RT) termination with auto calibration for single-ended I/O standards and on-chip differential termination (RD) for LVDS I/O standards on Left/Right I/O banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks.
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For more information, refer to the StratixIII Device I/O Features chapter.
External Memory Interfaces
The StratixIII I/O structure has been completely redesigned to provide flexibility and enable high-performance support for existing and emerging external memory standards such as DDR, DDR2, DDR3, QDRII, QDRII+, and RLDRAMII at frequencies of up to 533MHz.
Packed with features such as dynamic on-chip termination, trace mismatch
compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable DQ group widths, StratixIII I/Os supply the built-in functionality required for rapid and robust implementation of external memory interfaces. Double data-rate support is found on all sides of the StratixIII device. StratixIII devices provide an efficient architecture to quickly and easily fit wide external memory interfaces exactly where you want them.
A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the StratixIII device I/O, along with the QuartusII timing analysis tool (TimeQuest), provide the total solution for the highest reliable frequency of operation across process voltage and temperature.
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For more information about external memory interfaces, refer to the External Memory Interfaces in StratixIII Devices chapter.
High-Speed Differential I/O Interfaces with DPA
StratixIII devices contain dedicated circuitry for supporting differential standards at speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the
following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. StratixIII devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Architecture Features
The design security feature is available when configuring StratixIII FPGAs using the fast passive parallel (FPP) configuration mode with an external host (such as a MAXII device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes.
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For more information about the design security feature, refer to the Design Security in StratixIII Devices chapter.
SEU Mitigation
StratixIII devices have built-in error detection circuitry to detect data corruption due to soft errors in the configuration random-access memory (CRAM) cells. This feature allows all CRAM contents to be read and verified continuously during user mode operation to match a configuration-computed CRC value. The enhanced CRC circuit and frame-based configuration architecture allows detection and location of multiple, single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a reference design, allows don’t-care soft errors in the CRAM to be ignored during device operation. This provides a steep decrease in the effective soft error rate, increasing system reliability.
On-chip memory block SEU mitigation is also offered using the ninth bit and a configurable megafunction in the QuartusII software for MLAB and M9K blocks while the M144K memory blocks have built-in error correction code (ECC) circuitry.
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For more information about the dedicated error detection circuitry, refer to the SEU Mitigation in StratixIII Devices chapter.
Programmable Power
StratixIII delivers Programmable Power, the only FPGA with user programmable power options balancing today’s power and performance requirements. StratixIII devices utilize the most advanced power-saving techniques, including a variety of process, circuit, and architecture optimizations and innovations. In addition, user controllable power reduction techniques provide an optimal balance of performance and power reduction specific for each design configured into the StratixIII FPGA. The QuartusII software (starting from version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power-saving options available in the StratixIII FPGA without the need for any changes to the design flow.
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For more information about Programmable Power in StratixIII devices, refer to the following documents:
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Programmable Power and Temperature Sensing Diode in StratixIII Devices chapterAN 437: Power Optimization in StratixIII FPGAsStratixIII Programmable Power White Paper
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Chapter Revision History
Stratix III Device Handbook, Volume 1
2.Logic Array Blocks and Adaptive Logic
Modules in StratixIII Devices
SIII51002-1.5
Stratix III Device Handbook, Volume 1
4.TriMatrix Embedded Memory Blocks in
StratixIII Devices
SIII51004-1.8
Introduction
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of Stratix?III FPGA designs. TriMatrix memory includes 640- (in ROM mode only) or 320-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and 144-Kbit M144K blocks. The MLABs have been optimized to implement filter delay lines, small first-in first-out (FIFO) buffers, and shift registers. You can use the M9K blocks for general purpose memory applications, and the
M144K blocks are ideal for processor code storage, packet buffering, and video frame buffering.
You can independently configure each embedded memory block to be a single- or dual-port RAM, FIFO, ROM, or shift register via the Quartus?II
MegaWizardTMPlug-In Manager. You can stitch together multiple blocks of the same type to produce larger memories with minimal timing penalty. TriMatrix memory provides up to 20,491 Kbits of embedded SRAM at up to 600MHz operation. This chapter describes TriMatrix memory blocks, modes, features, and design considerations.
Overview
Table4–1 summarizes the features supported by the three sizes of TriMatrix memory.
Table4–1.Summary of TriMatrix Memory Features (Part 1 of 2)
FeatureMaximum performanceTotal memory bits (including parity bits)Configurations (depth × width)(1)MLABs600 MHz640 (in ROM mode) or 320 (in other modes)16×816×916×1016×1616×1816×20M9K Blocks580 MHz9,2168 K×14 K×22 K×41 K×81 K×9512×16512×18256×32256×36Parity bitsvvvM144K Blocks580 MHz147,45616 K×816 K×98 K×168 K×184 K×324 K×362 K×642 K×72Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2SGX130GF1508I4中文规格书 - 图文
