FPGA可编程逻辑器件芯片XC2S150-6FGG456C中文规格书 - 图文

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Spartan-3 FPGA Family: Functional Description

Configuration

Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are \others, indicated by the term \Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0, M1, and M2 are Dedicated pins. The mode pin settings are shown in Table26.Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings

Configuration Mode(1)Master Serial Slave SerialMaster Parallel Slave Parallel JTAGNotes:

1.2.

The voltage levels on the M0, M1, and M2 pins select the configuration mode.The daisy chain is possible only in the Serial modes when DOUT is used.

M001101

M101110

M201011

Synchronizing Clock

CCLK OutputCCLK InputCCLK OutputCCLK Input TCKInput

Data Width

11881

Serial DOUT(2)

YesYesNoNoNo

The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors

during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on the package style.

Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an externally generated clock.

A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.Table27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits. See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.Table 27:Spartan-3 FPGA Configuration Data

DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000

File Sizes439,2641,047,6161,699,1363,223,4885,214,7847,673,02411,316,86413,271,936

Xilinx Platform Flash PROM

Serial Configuration

XCF01SXCF01SXCF02SXCF04SXCF08PXCF08PXCF16PXCF16P

Parallel Configuration

XCF08PXCF08PXCF08PXCF08PXCF08PXCF08PXCF16PXCF16P

The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4Gbits), roughly equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Functional Description

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

Table 103:FG676 Package Pinout (Cont’d)

Bank000000000000000000000000000000000000000000

XC3S1000Pin NameIO_L09N_0IO_L09P_0IO_L10N_0IO_L10P_0N.C. (?)N.C. (?)N.C. (?)N.C. (?)IO_L15N_0IO_L15P_0IO_L16N_0IO_L16P_0N.C. (?)N.C. (?)N.C. (?)N.C. (?)IO_L19N_0IO_L19P_0IO_L22N_0IO_L22P_0N.C. (?)N.C. (?)IO_L24N_0IO_L24P_0IO_L25N_0IO_L25P_0N.C. (?)N.C. (?)IO_L27N_0IO_L27P_0IO_L28N_0IO_L28P_0IO_L29N_0IO_L29P_0IO_L30N_0IO_L30P_0IO_L31N_0