HIGH-SPEED RECEIVER ARCHITECTURE
申请(专利)号： US201916674957
专利号： US2020067600A1 主分类号： H04B10/50
申请日： 2019-11-05 公开公告日： 2020-02-27
分类号： H04B10/50;
申请权利人： 公开国代码： 优先权国家： INPHI
CORPORATION
US US
发明设计人： 申请国代码： 优先权： H04L5/16; H04B1/38; H04B10/69; H04L25/02; H04L25/03; H04B10/40; H03M13/41; H04B3/23; H04B7/005; H04B10/2507; H04B10/294 OSCAR ERNESTO
AGAZZI;
DIEGO ERNESTO CRIVELLI;
HUGO SANTIAGO CARRER;
MARIO RAFAEL HUEDA;
GERMAN CESAR AUGUSTO LUNA; CARL GRACE US
20191105 US
201916674957; 20180904 US 201816121293; 20171212 US 201715839380; 20161221 US 201615387246; 20140908 US 201414480085; 20110125 US 201113013149;
摘 要：
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. 主权项：
20101213 US 96698710; 20061114 US 55985006; 20061002 US 53802506; 20061020 US 55170106; 20100402 US 32031010; 20100125 US 29812510; 20060316 US 78334406; 20060303 US 77920006; 20051115 US 73710305; 20051003 US 72335705; 20060202 US 76486606
摘 要 附 图：
1. A receiver device, the device comprising:
HIGH-SPEED RECEIVER ARCHITECTURE
